From 4c5bc52ebb68e5e86075029c0c9ca1244bb759dc Mon Sep 17 00:00:00 2001
From: Kyle Cardoza <Kyle.Cardoza@gmail.com>
Date: Sat, 23 Mar 2024 20:45:21 -0400
Subject: [PATCH] Work on fleshing out sections

---
 Audio & Video.md | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/Audio & Video.md b/Audio & Video.md
index 2987b83..b08fdd2 100644
--- a/Audio & Video.md	
+++ b/Audio & Video.md	
@@ -66,17 +66,17 @@ VERA is configured and controlled using a series of 32 memory-mapped I/O registe
   <th>Bit&nbsp;0</th>
  </tr>
  <tr>
-  <td>$00</td>
+  <td>`0x00DF00`</td>
   <td>ADDRx_L (x=ADDRSEL)</td>
   <td colspan="8" align="center">VRAM Address (7:0)</td>
  </tr>
  <tr>
-  <td>$01</td>
+  <td>`0x00DF01`</td>
   <td>ADDRx_M (x=ADDRSEL)</td>
   <td colspan="8" align="center">VRAM Address (15:8)</td>
  </tr>
  <tr>
-  <td>$02</td>
+  <td>`0x00DF02`</td>
   <td>ADDRx_H (x=ADDRSEL)</td>
   <td colspan="4" align="center">Address Increment</td>
   <td colspan="1" align="center">DECR</td>
@@ -84,7 +84,7 @@ VERA is configured and controlled using a series of 32 memory-mapped I/O registe
   <td colspan="1" align="center">VRAM Address (16)</td>
  </tr>
  <tr>
-  <td>$03</td>
+  <td>`0x00DF03`</td>
   <td>DATA0</td>
   <td colspan="8" align="center">VRAM Data port 0</td>
  </tr>