Work on fleshing out sections
This commit is contained in:
parent
3ad81d9c9c
commit
4299060f52
|
@ -67,6 +67,7 @@ VERA is configured and controlled using a series of 32 memory-mapped I/O registe
|
|||
|
||||
<table>
|
||||
<tr>
|
||||
<th>Address: <pre>0x00DF00</pre></th>
|
||||
<th colspan="2">Address: <pre>0x00DF00</pre></th>
|
||||
<th>ADDR<em>x</em>_L (<em>x</em> = ADDRSEL)</th>
|
||||
</tr>
|
||||
</table>
|
||||
|
|
Loading…
Reference in New Issue