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Sentinel65X-Handbook
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Memory Management.md
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@ -27,24 +27,24 @@ The 16MB address space of Sentinel 65X is divided into regions as follows:
Each of the above regions is configured separately:
- Region 0 is controlled by bit 2 of the system speed control register (SSCR) located at `0x00DF41`. If that bit is clear, then region 0 selects the 512 byte SRAM on the CPU itself; if that bit is set, then region 0 selects the on-board 2MB SRAM chip.
- Region 1 selects the on-board 2MB SRAM chip as long as bit 5 of PCS7 (located at `0x00DF27`) is set and bit 3 is clear; otherwise, it will select nothing.
- Region 2 is controlled by PCS7 as well; if bit 4 of PCS7 is set, then this region selects ROM; which ROM is selected in this case is controlled by the /CART signal on the expansion/cartridge connector. If /CART is high, then the on-board 512KB flash ROM will be selected; otherwise, the cartridge ROM connected to /ROM1 is selected instead.
- Region 1 selects the on-board 2MB SRAM chip as long as bit 5 of `PCS7` (located at `0x00DF27`) is set and bit 3 is clear; otherwise, it will select nothing.
- Region 2 is controlled by `PCS7` as well; if bit 4 of `PCS7` is set, then this region selects ROM; which ROM is selected in this case is controlled by the /CART signal on the expansion/cartridge connector. If /CART is high, then the on-board 512KB flash ROM will be selected; otherwise, the cartridge ROM connected to /ROM1 is selected instead.
- Region 3 is dedicated to the I/O space for the VERA chip.
- Region 4 is dedicated to on-CPU integrated peripheral devices.
- Region 5 is dedicated to the I/O space for the clock port.
- Region 6 is controlled by bit 7 of BCR, located at `0x00DF40`. If that bit is clear, then the on-CPU mask ROM is selected. If that bit is set, then if bit 4 of PCS7 is set, then on-board flash ROM will be selected; otherwise, if bit 5 of PCS7 is set, then the on-board 2MB SRAM will be selected; otherwise, nothing will be selected.
- Region 7 is controlled by bit 5 of PCS7; if that bit is set, then the 2MB SRAM will be selected, otherwise nothing will be selected.
- Region 8 is also controlled by bit 5 of PCS7; if that bit is set, then the optional 2MB expansion RAM is selected, if present; otherwise, nothing is selected.
- Region 9 is controlled by bit 6 of PCS7; if that bit is set, then expansion space is selected. This region is dedicated to user expansions.
- Region 10 is controlled by bit 7 of PCS7. If that bit is set, then this region will select the on-board 512KB flash ROM. Otherwise, nothing will be selected.
- Region 11 is also controlled by bit 7 of PCS7. If that bit is set, then this region will select the expansion ROM, if installed. Otherwise, nothing will be selected. Note that if bits 4 and 7 of PCS7 are set, then the regions `0x008000` to `0x00DEFF` and `0xC08000` to `0xC0DEFF` will be mapped to the same area of ROM; if bit 7 of BCR is also set, then the regions `0x00E000` to `0x00FFFF` and `0xC0E000` to `0xC0FFFF` will also be mapped to the same physical memory.
- Region 6 is controlled by bit 7 of `BCR`, located at `0x00DF40`. If that bit is clear, then the on-CPU mask ROM is selected. If that bit is set, then if bit 4 of `PCS7` is set, then on-board flash ROM will be selected; otherwise, if bit 5 of `PCS7` is set, then the on-board 2MB SRAM will be selected; otherwise, nothing will be selected.
- Region 7 is controlled by bit 5 of `PCS7`; if that bit is set, then the 2MB SRAM will be selected, otherwise nothing will be selected.
- Region 8 is also controlled by bit 5 of `PCS7`; if that bit is set, then the optional 2MB expansion RAM is selected, if present; otherwise, nothing is selected.
- Region 9 is controlled by bit 6 of `PCS7`; if that bit is set, then expansion space is selected. This region is dedicated to user expansions.
- Region 10 is controlled by bit 7 of `PCS7`. If that bit is set, then this region will select the on-board 512KB flash ROM. Otherwise, nothing will be selected.
- Region 11 is also controlled by bit 7 of `PCS7`. If that bit is set, then this region will select the expansion ROM, if installed. Otherwise, nothing will be selected. Note that if bits 4 and 7 of `PCS7` are set, then the regions `0x008000` to `0x00DEFF` and `0xC08000` to `0xC0DEFF` will be mapped to the same area of ROM; if bit 7 of `BCR` is also set, then the regions `0x00E000` to `0x00FFFF` and `0xC0E000` to `0xC0FFFF` will also be mapped to the same physical memory.
Note that in the case that "nothing" is selected for a given address range, then user expansions are free to decode and make use of that address space for themselves.
In the case of memory regions 2 and 6, if bits 4 and 5 of PCS7 are both set, any attempt to select that region for reading will read the ROM, and any attemt to write to that region will write to the on-board SRAM.
In the case of memory regions 2 and 6, if bits 4 and 5 of `PCS7` are both set, any attempt to select that region for reading will read the ROM, and any attemt to write to that region will write to the on-board SRAM.
## Main RAM
Sentinel 65X comes with 2MB of fast static RAM on the board. This memory is available in both 6502 emulation mode (in which only addresses from 0x0000 to 0xffff are valid) and in 65816 native mode.
Sentinel 65X comes with 2MB of fast static RAM on the board. This memory is available in both 6502 emulation mode (in which only addresses from `0x0000` to `0xffff` are valid) and in 65816 native mode.
## Main ROM
@ -83,6 +83,6 @@ This configuration is sufficient for most use cases, as all on-board hardware is
The Sentinel 65X cartridge port can accept cartridges with RAM, ROM, or memory-mapped I/O devices, mapping to the above-mentioned regions based on the specific pins of the cartridge port used to select the hardware on the cartridge. The expansion backplane, when installed, will allow the same behaviour with expansion cards.
By tying cartridge or expansion port pin b31, labeled /CART, to ground, a cartridge can be booted instead of the on-board flash ROM, as this will cause region 2 to be mapped to the /ROM1 pin on the cartridge connector. In this case, the cartridge ROM connected to the /ROM1 pin must have the ASCII value "WDC" beginning at offset 0x008000. If this is present, then ROM code will begin executing at offset 0x008004. It is usually advisable for the early boot code on a bootable ROM cartridge to set bit 4 of PCS7, which will map that same expansion ROM into region 6.
By tying cartridge or expansion port pin `b31`, labeled `/CART`, to ground, a cartridge can be booted instead of the on-board flash ROM, as this will cause region 2 to be mapped to the `/ROM1` pin on the cartridge connector. In this case, the cartridge ROM connected to the `/ROM1` pin must have the ASCII value "WDC" beginning at offset `0x008000`. If this is present, then ROM code will begin executing at offset `0x008004`. It is usually advisable for the early boot code on a bootable ROM cartridge to set bit 4 of `PCS7`, which will map that same expansion ROM into region 6.
A cartridge or expansion which contains ROM does not necessarily need to be bootable, if it is intended as an accessory to software loaded from some other device.