Sentinel65X
/
Sentinel65X-Handbook
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Work on formatting

This commit is contained in:
Kyle Cardoza 2024-03-22 01:27:41 -04:00
parent ce3e9edb35
commit 4782dfeaf2
1 changed files with 16 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
Memory Management.md
View File

@ -11,33 +11,33 @@ Sentinel 65X, having a [65816-compatible CPU](CPU.md), has a 24-bit address bus,
The 16MB address space of Sentinel 65X is divided into regions as follows:
- Region 0: `0x000000` to 0x0001FF 512 Bytes
- Region 1: 0x000200 to 0x007FFF 32,256 Bytes
- Region 2: 0x008000 to 0x00DEFF 24,320 Bytes
- Region 3: 0x00DF00 to 0x00DF1F 32 Bytes
- Region 4: 0x00DF20 to 0x00DFBF 160 Bytes
- Region 5: 0x00DFC0 to 0x00DFFF 64 Bytes
- Region 6: 0x00E000 to 0x00FFFF 8,192 Bytes
- Region 7: 0x010000 to 0x19FFFF 2,031,616 Bytes
- Region 8: 0x200000 to 0x3FFFFF 2,097,152 Bytes
- Region 9: 0x400000 to 0xBFFFFF 8,388,608 Bytes
- Region 10: 0xC00000 to 0xC7FFFF 524,288 Bytes
- Region 11: 0xC80000 to 0xFFFFFF 3,670,016 Bytes
- Region 0: `0x000000` to `0x0001FF` 512 Bytes
- Region 1: `0x000200` to `0x007FFF` 32,256 Bytes
- Region 2: `0x008000` to `0x00DEFF` 24,320 Bytes
- Region 3: `0x00DF00` to `0x00DF1F` 32 Bytes
- Region 4: `0x00DF20` to `0x00DFBF` 160 Bytes
- Region 5: `0x00DFC0` to `0x00DFFF` 64 Bytes
- Region 6: `0x00E000` to `0x00FFFF` 8,192 Bytes
- Region 7: `0x010000` to `0x19FFFF` 2,031,616 Bytes
- Region 8: `0x200000` to `0x3FFFFF` 2,097,152 Bytes
- Region 9: `0x400000` to `0xBFFFFF` 8,388,608 Bytes
- Region 10: `0xC00000` to `0xC7FFFF` 524,288 Bytes
- Region 11: `0xC80000` to `0xFFFFFF` 3,670,016 Bytes
Each of the above regions is configured separately:
- Region 0 is controlled by bit 2 of the system speed control register (SSCR) located at 0x00DF41. If that bit is clear, then region 0 selects the 512 byte SRAM on the CPU itself; if that bit is set, then region 0 selects the on-board 2MB SRAM chip.
- Region 1 selects the on-board 2MB SRAM chip as long as bit 5 of PCS7 (located at 0x00DF27) is set and bit 3 is clear; otherwise, it will select nothing.
- Region 0 is controlled by bit 2 of the system speed control register (SSCR) located at `0x00DF41`. If that bit is clear, then region 0 selects the 512 byte SRAM on the CPU itself; if that bit is set, then region 0 selects the on-board 2MB SRAM chip.
- Region 1 selects the on-board 2MB SRAM chip as long as bit 5 of PCS7 (located at `0x00DF27`) is set and bit 3 is clear; otherwise, it will select nothing.
- Region 2 is controlled by PCS7 as well; if bit 4 of PCS7 is set, then this region selects ROM; which ROM is selected in this case is controlled by the /CART signal on the expansion/cartridge connector. If /CART is high, then the on-board 512KB flash ROM will be selected; otherwise, the cartridge ROM connected to /ROM1 is selected instead.
- Region 3 is dedicated to the I/O space for the VERA chip.
- Region 4 is dedicated to on-CPU integrated peripheral devices.
- Region 5 is dedicated to the I/O space for the clock port.
- Region 6 is controlled by bit 7 of BCR, located at 0x00DF40. If that bit is clear, then the on-CPU mask ROM is selected. If that bit is set, then if bit 4 of PCS7 is set, then on-board flash ROM will be selected; otherwise, if bit 5 of PCS7 is set, then the on-board 2MB SRAM will be selected; otherwise, nothing will be selected.
- Region 6 is controlled by bit 7 of BCR, located at `0x00DF40`. If that bit is clear, then the on-CPU mask ROM is selected. If that bit is set, then if bit 4 of PCS7 is set, then on-board flash ROM will be selected; otherwise, if bit 5 of PCS7 is set, then the on-board 2MB SRAM will be selected; otherwise, nothing will be selected.
- Region 7 is controlled by bit 5 of PCS7; if that bit is set, then the 2MB SRAM will be selected, otherwise nothing will be selected.
- Region 8 is also controlled by bit 5 of PCS7; if that bit is set, then the optional 2MB expansion RAM is selected, if present; otherwise, nothing is selected.
- Region 9 is controlled by bit 6 of PCS7; if that bit is set, then expansion space is selected. This region is dedicated to user expansions.
- Region 10 is controlled by bit 7 of PCS7. If that bit is set, then this region will select the on-board 512KB flash ROM. Otherwise, nothing will be selected.
- Region 11 is also controlled by bit 7 of PCS7. If that bit is set, then this region will select the expansion ROM, if installed. Otherwise, nothing will be selected. Note that if bits 4 and 7 of PCS7 are set, then the regions 0x008000 to 0x00DEFF and 0xC08000 to 0xC0DEFF will be mapped to the same area of ROM; if bit 7 of BCR is also set, then the regions 0x00E000 to 0x00FFFF and 0xC0E000 to 0xC0FFFF will also be mapped to the same physical memory.
- Region 11 is also controlled by bit 7 of PCS7. If that bit is set, then this region will select the expansion ROM, if installed. Otherwise, nothing will be selected. Note that if bits 4 and 7 of PCS7 are set, then the regions `0x008000` to `0x00DEFF` and `0xC08000` to `0xC0DEFF` will be mapped to the same area of ROM; if bit 7 of BCR is also set, then the regions `0x00E000` to `0x00FFFF` and `0xC0E000` to `0xC0FFFF` will also be mapped to the same physical memory.
Note that in the case that "nothing" is selected for a given address range, then user expansions are free to decode and make use of that address space for themselves.
In the case of memory regions 2 and 6, if bits 4 and 5 of PCS7 are both set, any attempt to select that region for reading will read the ROM, and any attemt to write to that region will write to the on-board SRAM.