Work on fleshing out sections
This commit is contained in:
parent
56dff0f483
commit
123fbf56f5
|
@ -351,6 +351,21 @@ Sprites are controlled using 128 control entries, beginning at VERA address `0x1
|
||||||
</tr>
|
</tr>
|
||||||
</table>
|
</table>
|
||||||
|
|
||||||
|
The bitmap address of a sprite is the top 12 bits of a 17-bit VERA memory address; the low order 5 bits are always `0`, which means that sprite data is always aligned to a 32-byte boundary.
|
||||||
|
|
||||||
|
The X and Y positions are 10-bit numbers representing the offset from the screen origin of the sprite's origin.
|
||||||
|
|
||||||
|
`FIXME: How does the collision mask work?`
|
||||||
|
|
||||||
|
The layer position value determines the drawing order of the sprite relative to the two tile/bitmap layers:
|
||||||
|
|
||||||
|
| Value | Description |
|
||||||
|
| :---: | :------------: |
|
||||||
|
| 0 | Disabled |
|
||||||
|
| 1 | Below layer 0 |
|
||||||
|
| 2 | Between layers |
|
||||||
|
| 3 | Above layer 1 |
|
||||||
|
|
||||||
## 16-Bit Reads/Writes
|
## 16-Bit Reads/Writes
|
||||||
|
|
||||||
With appropriate configuration of registers, it is possible to perform sequential 16-bit reads and writes to VERA address space:
|
With appropriate configuration of registers, it is possible to perform sequential 16-bit reads and writes to VERA address space:
|
||||||
|
|
Loading…
Reference in New Issue