Sentinel65X-Handbook/CPU.md

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# CPU

Sentinel 65X uses the [WDC W65C265S](https://www.westerndesigncenter.com/wdc/w65c265s-chip.php) CPU from [Western Design Center](https://www.westerndesigncenter.com) as its main processor.

## Features

- Support for all [65C02](https://www.westerndesigncenter.com/wdc/w65c02s-chip.php) and [65C816](https://www.westerndesigncenter.com/wdc/w65c816s-chip.php) opcodes
- Non-multiplexed 24-bit address bus
- 8-bit data bus
- 7 pre-decoded chip select outputs
- 16MB linear address space
- 29 priority-encoded vectored interrupts
- 8 timer/counters

## Address Bus

The 24-bit address bus in the W65C265S, unlike that of the W65C816S, is not multiplexed -- no external logic is required to separate the address signals from the data bus.

Additionally, the seven built-in chip selects are hard-wired to decode specific memory regions. The address decoding logic provided by the CPU is supplemented in Sentinel 65X by an ATF22LV16 programmable logic device, which handles essential glue logic functions not provided by the CPU itself.

See the section on [memory management](Memory%20Management.md) for details on address decoding.

## Logic Levels

All logic signals on Sentinel 65X are specified as CMOS-compatible, 3.3V VCC.

## References

- [W65C265S Datasheet](https://www.westerndesigncenter.com/wdc/documentation/w65c265s.pdf)