Sentinel65X-Handbook/CPU.md

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# CPU

Sentinel 65X uses the WDC W65C265S CPU from Western Design Center as its main processor. This chip features:

- Support for all 65C02 and 65C816 opcodes
- Non-multiplexed 24-bit address bus
- 8-bit data bus
- 7 pre-decoded chip select outputs
- 16MB linear address space
- 29 priority-encoded vectored interrupts
- 8 timer/counters

The address decoding logic provided by the CPU is supplemented in Sentinel 65X by an ATF22LV16 programmable logic device, which handles essential glue logic functions not provided by the CPU itself.

See the section on [memory management]("Memory Management.md") for details on address decoding.
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Added sections 2024-03-22 06:18:23 +01:00			`# CPU`
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			`Sentinel 65X uses the WDC W65C265S CPU from Western Design Center as its main processor. This chip features:`

			`- Support for all 65C02 and 65C816 opcodes`
			`- Non-multiplexed 24-bit address bus`
			`- 8-bit data bus`
			`- 7 pre-decoded chip select outputs`
			`- 16MB linear address space`
			`- 29 priority-encoded vectored interrupts`
			`- 8 timer/counters`

			`The address decoding logic provided by the CPU is supplemented in Sentinel 65X by an ATF22LV16 programmable logic device, which handles essential glue logic functions not provided by the CPU itself.`

Work on fleshing out sections 2024-03-23 04:02:45 +01:00			`See the section on [memory management]("Memory Management.md") for details on address decoding.`