Refactored CPU_run
This commit is contained in:
Rebecca Buckingham
parent
cafbf52f2f
commit
f4653891c7
354
src/dispatch.c
354
src/dispatch.c
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@ -8,6 +8,9 @@
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* Copyright (C) 2006 by Samuel A. Falvo II
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*
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* Modified for greater portability and virtual hardware independence.
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*
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* Copyright (C) 2024 by Rebecca Buckingham
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* highly modified to integrate with bsx emulator.
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*/
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#define CPU_DISPATCH
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@ -15,10 +18,7 @@
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#include "cpu.h"
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#include "cpumicro.h"
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#include "util.h"
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//#define LIMIT_INSTRUCTION_COUNT 10000
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//void CPUEvent_elapse( word32 cycles );
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#include <stdint.h>
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int dispatch_quit = 0;
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@ -45,216 +45,164 @@ union {
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duala atmp,opaddr;
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dualw wtmp,otmp,operand;
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int a1,a2,a3,a4,o1,o2,o3,o4;
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#ifdef OLDCYCLES
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byte *cpu_curr_cycle_table;
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#endif
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void (**cpu_curr_opcode_table)();
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extern int cpu_reset,cpu_abort,cpu_nmi,cpu_irq,cpu_stop,cpu_wait,cpu_trace;
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extern int cpu_update_period;
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extern int cpu_irne64,cpu_irqt5;
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extern int cpu_update_period;
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extern void (*cpu_opcode_table[1310])();
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#ifdef OLDCYCLES
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/* Base cycle counts for all possible 1310 opcodes (262 opcodes x 5 modes). */
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/* The opcode handlers may add additional cycles to handle special cases such */
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/* a non-page-aligned direct page register or taking a branch. */
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uint64_t last_update, next_update;
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byte cpu_cycle_table[1310] =
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{
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8, 6, 8, 4, 5, 3, 5, 6, 3, 2, 2, 4, 6, 4, 6, 5, /* e=0, m=1, x=1 */
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2, 5, 5, 7, 5, 4, 6, 6, 2, 4, 2, 2, 6, 4, 7, 5,
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6, 6, 8, 4, 3, 3, 5, 6, 4, 2, 2, 5, 4, 4, 6, 5,
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2, 5, 5, 7, 4, 4, 6, 6, 2, 4, 2, 2, 4, 4, 7, 5,
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7, 6, 2, 4, 7, 3, 5, 6, 3, 2, 2, 3, 3, 4, 6, 5,
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2, 5, 5, 7, 7, 4, 6, 6, 2, 4, 3, 2, 4, 4, 7, 5,
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6, 6, 6, 4, 3, 3, 5, 6, 4, 2, 2, 6, 5, 4, 6, 5,
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2, 5, 5, 7, 4, 4, 6, 6, 2, 4, 4, 2, 6, 4, 7, 5,
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2, 6, 3, 4, 3, 3, 3, 6, 2, 2, 2, 3, 4, 4, 4, 5,
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2, 6, 5, 7, 4, 4, 4, 6, 2, 5, 2, 2, 4, 5, 5, 5,
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2, 6, 2, 4, 3, 3, 3, 6, 2, 2, 2, 4, 4, 4, 4, 5,
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2, 5, 5, 7, 4, 4, 4, 6, 2, 4, 2, 2, 4, 4, 4, 5,
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2, 6, 3, 4, 3, 3, 5, 6, 2, 2, 2, 3, 4, 4, 4, 5,
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2, 5, 5, 7, 6, 4, 6, 6, 2, 4, 3, 3, 6, 4, 7, 5,
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2, 6, 3, 4, 3, 3, 5, 6, 2, 2, 2, 3, 4, 4, 6, 5,
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2, 5, 5, 7, 5, 4, 6, 6, 2, 4, 4, 2, 6, 4, 7, 5,
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0, 0, 0, 0, 0, 0,
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#define RESET_OP 256
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#define ABORT_OP 257
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#define NMI_OP 258
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#define IRQ_OP 259
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#define IRNE64_OP 260
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#define IRQT5_OP 261
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8, 6, 8, 4, 5, 3, 5, 6, 3, 2, 2, 4, 6, 4, 6, 5, /* e=0, m=1, x=0 */
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2, 6, 5, 7, 5, 4, 6, 6, 2, 5, 2, 2, 6, 5, 7, 5,
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6, 6, 8, 4, 3, 3, 5, 6, 4, 2, 2, 5, 4, 4, 6, 5,
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2, 6, 5, 7, 4, 4, 6, 6, 2, 5, 2, 2, 5, 5, 7, 5,
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7, 6, 2, 4, 0, 3, 5, 6, 4, 2, 2, 3, 3, 4, 6, 5,
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2, 6, 5, 7, 0, 4, 6, 6, 2, 5, 4, 2, 4, 5, 7, 5,
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6, 6, 6, 4, 3, 3, 5, 6, 5, 2, 2, 6, 5, 4, 6, 5,
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2, 6, 5, 7, 4, 4, 6, 6, 2, 5, 5, 2, 6, 5, 7, 5,
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2, 6, 3, 4, 4, 3, 4, 6, 2, 2, 2, 3, 5, 4, 5, 5,
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2, 6, 5, 7, 5, 4, 5, 6, 2, 5, 2, 2, 4, 5, 5, 5,
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3, 6, 3, 4, 4, 3, 4, 6, 2, 2, 2, 4, 5, 4, 5, 5,
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2, 6, 5, 7, 5, 4, 5, 6, 2, 5, 2, 2, 5, 5, 5, 5,
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3, 6, 3, 4, 4, 3, 6, 6, 2, 2, 2, 3, 5, 4, 6, 5,
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2, 6, 5, 7, 6, 4, 8, 6, 2, 5, 4, 3, 6, 5, 7, 5,
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3, 6, 3, 4, 4, 3, 6, 6, 2, 2, 2, 3, 5, 4, 6, 5,
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2, 6, 5, 7, 5, 4, 8, 6, 2, 5, 5, 2, 6, 5, 7, 5,
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0, 0, 0, 0, 0, 0,
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8, 7, 8, 5, 7, 4, 7, 7, 3, 3, 2, 4, 8, 5, 8, 6, /* e=0, m=0, x=1 */
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2, 6, 6, 8, 7, 5, 8, 7, 2, 5, 2, 2, 8, 5, 9, 6,
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6, 7, 8, 5, 4, 4, 7, 7, 4, 3, 2, 5, 5, 5, 8, 6,
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2, 6, 6, 8, 5, 5, 8, 7, 2, 5, 2, 2, 5, 5, 9, 6,
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7, 7, 2, 5, 0, 4, 7, 7, 4, 3, 2, 3, 3, 5, 8, 6,
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2, 6, 6, 8, 0, 5, 8, 7, 2, 5, 3, 2, 4, 5, 9, 6,
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6, 7, 6, 5, 4, 4, 7, 7, 5, 3, 2, 6, 5, 5, 8, 6,
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2, 6, 6, 8, 5, 5, 8, 7, 2, 5, 4, 2, 6, 5, 9, 6,
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2, 7, 3, 5, 3, 4, 3, 7, 2, 3, 2, 3, 4, 5, 4, 6,
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2, 6, 6, 8, 4, 5, 4, 7, 2, 5, 2, 2, 5, 5, 5, 6,
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2, 7, 2, 5, 3, 4, 3, 7, 2, 3, 2, 4, 4, 5, 4, 6,
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2, 6, 6, 8, 4, 5, 4, 7, 2, 5, 2, 2, 4, 5, 4, 6,
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2, 7, 3, 5, 3, 4, 7, 7, 2, 3, 2, 3, 4, 5, 8, 6,
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2, 6, 6, 8, 6, 5, 8, 7, 2, 5, 3, 3, 6, 5, 9, 6,
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2, 7, 3, 5, 3, 4, 7, 7, 2, 3, 2, 3, 4, 5, 8, 6,
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2, 6, 6, 8, 5, 5, 8, 7, 2, 5, 4, 2, 6, 5, 9, 6,
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0, 0, 0, 0, 0, 0,
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8, 7, 8, 5, 7, 4, 7, 7, 3, 3, 2, 4, 8, 5, 8, 6, /* e=0, m=0, x=0 */
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2, 7, 6, 8, 7, 5, 8, 7, 2, 6, 2, 2, 8, 6, 9, 6,
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6, 7, 8, 5, 4, 4, 7, 7, 4, 3, 2, 5, 5, 5, 8, 6,
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2, 7, 6, 8, 5, 5, 8, 7, 2, 6, 2, 2, 6, 6, 9, 6,
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7, 7, 2, 5, 0, 4, 7, 7, 3, 3, 2, 3, 3, 5, 8, 6,
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2, 7, 6, 8, 0, 5, 8, 7, 2, 6, 4, 2, 4, 6, 9, 6,
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6, 7, 6, 5, 4, 4, 7, 7, 4, 3, 2, 6, 5, 5, 8, 6,
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2, 7, 6, 8, 5, 5, 8, 7, 2, 6, 5, 2, 6, 6, 9, 6,
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2, 7, 3, 5, 4, 4, 4, 7, 2, 3, 2, 3, 5, 5, 5, 6,
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2, 7, 6, 8, 5, 5, 5, 7, 2, 6, 2, 2, 5, 6, 6, 6,
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3, 7, 3, 5, 4, 4, 4, 7, 2, 3, 2, 4, 5, 5, 5, 6,
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2, 7, 6, 8, 5, 5, 5, 7, 2, 6, 2, 2, 5, 6, 5, 6,
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3, 7, 3, 5, 4, 4, 7, 7, 2, 3, 2, 3, 5, 5, 8, 6,
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2, 7, 6, 8, 6, 5, 8, 7, 2, 6, 4, 3, 6, 6, 9, 6,
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3, 7, 3, 5, 4, 4, 7, 7, 2, 3, 2, 3, 5, 5, 8, 6,
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2, 7, 6, 8, 5, 5, 8, 7, 2, 6, 5, 2, 6, 6, 9, 6,
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0, 0, 0, 0, 0, 0,
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8, 6, 8, 4, 5, 3, 5, 6, 3, 2, 2, 4, 6, 4, 6, 5, /* e=1, m=1, x=1 */
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2, 5, 5, 7, 5, 4, 6, 6, 2, 4, 2, 2, 6, 4, 7, 5,
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6, 6, 8, 4, 3, 3, 5, 6, 4, 2, 2, 5, 4, 4, 6, 5,
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2, 5, 5, 7, 4, 4, 6, 6, 2, 4, 2, 2, 4, 4, 7, 5,
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7, 6, 2, 4, 0, 3, 5, 6, 3, 2, 2, 3, 3, 4, 6, 5,
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2, 5, 5, 7, 0, 4, 6, 6, 2, 4, 3, 2, 4, 4, 7, 5,
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6, 6, 6, 4, 3, 3, 5, 6, 4, 2, 2, 6, 5, 4, 6, 5,
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2, 5, 5, 7, 4, 4, 6, 6, 2, 4, 4, 2, 6, 4, 7, 5,
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2, 6, 3, 4, 3, 3, 3, 6, 2, 2, 2, 3, 4, 4, 4, 5,
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2, 5, 5, 7, 4, 4, 4, 6, 2, 4, 2, 2, 4, 4, 4, 5,
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2, 6, 2, 4, 3, 3, 3, 6, 2, 2, 2, 4, 4, 4, 4, 5,
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2, 5, 5, 7, 4, 4, 4, 6, 2, 4, 2, 2, 4, 4, 4, 5,
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2, 6, 3, 4, 3, 3, 5, 6, 2, 2, 2, 3, 4, 4, 6, 5,
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2, 5, 5, 7, 6, 4, 6, 6, 2, 4, 3, 3, 6, 4, 7, 5,
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2, 6, 3, 4, 3, 3, 5, 6, 2, 2, 2, 3, 4, 4, 6, 5,
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2, 5, 5, 7, 5, 4, 6, 6, 2, 4, 4, 2, 6, 4, 7, 5,
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0, 0, 0, 0, 0, 0
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};
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#endif
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void CPU_run(void)
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{
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word32 last_update,next_update;
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int opcode;
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#ifdef LIMIT_INSTRUCTION_COUNT
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long instructionCount = 0;
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#endif
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cpu_cycle_count = 0;
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last_update = 0;
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next_update = cpu_update_period;
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E = 1;
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F_setM(1);
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F_setX(1);
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CPU_modeSwitch();
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dispatch:
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// CPUEvent_elapse( cpu_cycle_count );
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// cpu_cycle_count = 0;
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if (dispatch_quit)
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return;
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// TODO remove this.
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#ifdef LIMIT_INSTRUCTION_COUNT
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instructionCount++;
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if (instructionCount > LIMIT_INSTRUCTION_COUNT)
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return;
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#endif
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// #ifdef E_UPDATE
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if (cpu_cycle_count >= next_update) goto update;
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update_resume:
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// #endif
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#ifdef DEBUG
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if (cpu_trace) goto debug;
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debug_resume:
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#endif
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if (cpu_reset) goto reset;
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if (cpu_stop) goto dispatch;
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if (cpu_abort) goto abort;
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if (cpu_nmi) goto nmi;
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if (cpu_irq) goto irq;
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if (cpu_irne64) goto irne64;
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if (cpu_irqt5) goto irqt5;
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irq_return:
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if (cpu_wait) { cpu_cycle_count++; goto dispatch; }
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opcode = M_READ_OPCODE(PC.A);
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PC.W.PC++;
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#ifdef OLDCYCLES
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cpu_cycle_count += cpu_curr_cycle_table[opcode];
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#endif
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(**cpu_curr_opcode_table[opcode])();
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goto dispatch;
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/* Special cases. Since these don't happen a lot more often than they */
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/* do happen, accessing them this way means most of the time the */
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/* generated code is _not_ branching. Only during the special cases do */
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/* we take the branch penalty (if there is one). */
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// #ifdef E_UPDATE
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update:
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E_UPDATE(cpu_cycle_count);
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last_update = cpu_cycle_count;
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next_update = last_update + cpu_update_period;
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goto update_resume;
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// #endif
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#ifdef DEBUG
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debug:
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CPU_debug();
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goto debug_resume;
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#endif
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reset:
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(**cpu_curr_opcode_table[256])();
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goto dispatch;
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abort:
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(**cpu_curr_opcode_table[257])();
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goto dispatch;
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nmi:
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(**cpu_curr_opcode_table[258])();
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goto dispatch;
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irq:
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if (P & 0x04) goto irq_return;
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(**cpu_curr_opcode_table[259])();
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goto dispatch;
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irne64:
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if (P & 0x04) goto irq_return;
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(**cpu_curr_opcode_table[260])();
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goto dispatch;
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irqt5:
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if (P & 0x04) goto irq_return;
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(**cpu_curr_opcode_table[261])();
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goto dispatch;
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void handleSignal(int type) {
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(**cpu_curr_opcode_table[type])();
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}
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void doUpdate() {
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E_UPDATE(cpu_cycle_count);
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last_update = cpu_cycle_count;
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next_update = last_update + cpu_update_period;
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}
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void CPU_init(void) {
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last_update = 0;
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next_update = cpu_update_period;
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cpu_cycle_count = 0;
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E = 1;
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F_setM(1);
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F_setX(1);
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CPU_modeSwitch();
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}
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void CPU_step(void) {
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if (cpu_cycle_count >= next_update) doUpdate();
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int opcode = M_READ_OPCODE(PC.A);
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PC.W.PC++;
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(**cpu_curr_opcode_table[opcode])();
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}
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void CPU_run(void) {
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while (!dispatch_quit) {
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if (cpu_trace) CPU_debug();
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if (cpu_reset) { handleSignal(RESET_OP); continue; }
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if (cpu_abort) { handleSignal(ABORT_OP); continue; }
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if (cpu_nmi) { handleSignal(NMI_OP); continue; }
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if (cpu_irq) { handleSignal(IRQ_OP); continue; }
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if (cpu_irne64) { handleSignal(IRNE64_OP); continue; }
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if (cpu_irqt5) { handleSignal(IRQT5_OP); continue; }
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if (cpu_wait) { cpu_cycle_count++; continue; }
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if (cpu_stop) continue;
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CPU_step();
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}
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}
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// void old_CPU_run(void)
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// {
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// word32 last_update,next_update;
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// int opcode;
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// #ifdef LIMIT_INSTRUCTION_COUNT
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// long instructionCount = 0;
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// #endif
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// cpu_cycle_count = 0;
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// last_update = 0;
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// next_update = cpu_update_period;
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// E = 1;
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// F_setM(1);
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// F_setX(1);
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// CPU_modeSwitch();
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// dispatch:
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// // CPUEvent_elapse( cpu_cycle_count );
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// // cpu_cycle_count = 0;
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// if (dispatch_quit)
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// return;
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// // TODO remove this.
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// #ifdef LIMIT_INSTRUCTION_COUNT
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// instructionCount++;
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// if (instructionCount > LIMIT_INSTRUCTION_COUNT)
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// return;
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// #endif
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// // #ifdef E_UPDATE
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// if (cpu_cycle_count >= next_update) goto update;
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// update_resume:
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// // #endif
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// #ifdef DEBUG
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// if (cpu_trace) goto debug;
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// debug_resume:
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// #endif
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// if (cpu_reset) goto reset;
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// if (cpu_stop) goto dispatch;
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// if (cpu_abort) goto abort;
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// if (cpu_nmi) goto nmi;
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// if (cpu_irq) goto irq;
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// if (cpu_irne64) goto irne64;
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// if (cpu_irqt5) goto irqt5;
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// irq_return:
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// if (cpu_wait) { cpu_cycle_count++; goto dispatch; }
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// opcode = M_READ_OPCODE(PC.A);
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// PC.W.PC++;
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// #ifdef OLDCYCLES
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// cpu_cycle_count += cpu_curr_cycle_table[opcode];
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// #endif
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// (**cpu_curr_opcode_table[opcode])();
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// goto dispatch;
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// /* Special cases. Since these don't happen a lot more often than they */
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// /* do happen, accessing them this way means most of the time the */
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// /* generated code is _not_ branching. Only during the special cases do */
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// /* we take the branch penalty (if there is one). */
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// // #ifdef E_UPDATE
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// update:
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// E_UPDATE(cpu_cycle_count);
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// last_update = cpu_cycle_count;
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// next_update = last_update + cpu_update_period;
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// goto update_resume;
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// // #endif
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// #ifdef DEBUG
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// debug:
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// CPU_debug();
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// goto debug_resume;
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// #endif
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// reset:
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// (**cpu_curr_opcode_table[256])();
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// goto dispatch;
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// abort:
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// (**cpu_curr_opcode_table[257])();
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// goto dispatch;
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// nmi:
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// (**cpu_curr_opcode_table[258])();
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// goto dispatch;
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// irq:
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// if (P & 0x04) goto irq_return;
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// (**cpu_curr_opcode_table[259])();
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// goto dispatch;
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// irne64:
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// if (P & 0x04) goto irq_return;
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// (**cpu_curr_opcode_table[260])();
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||||
// goto dispatch;
|
||||
// irqt5:
|
||||
// if (P & 0x04) goto irq_return;
|
||||
// (**cpu_curr_opcode_table[261])();
|
||||
// goto dispatch;
|
||||
// }
|
||||
|
||||
/* Recalculate opcode_offset based on the new processor mode */
|
||||
|
||||
void CPU_modeSwitch(void) {
|
||||
|
|
|
|||
|
|
@ -26,7 +26,6 @@ void EMUL_hardwareUpdate(word32 timestamp) {
|
|||
}
|
||||
|
||||
if (SDL_PollEvent(&sdl_event)) {
|
||||
puts("got an event!");
|
||||
handleEvent(&sdl_event);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue