Audio & Video

The VERA FPGA core, implemented on an iCE40 FPGA, is used to generate all audio and video signals produced by Sentinel 65X. This core, developed for the Commander X16 project by Frank van den Hoef, is licensed under the MIT license. It has been modified by Brian Swetland for Sentinel 65X, including porting it to be built using the Yosys open-source FPGA toolchain.

Video

The VERA video generator outputs a fixed 640x480, 60Hz digital RGB signal, with a total of 4,096 possible colours, using a 12-bit R4G4B4 colour space.

The video generation is done using two independent tile/bitmap layers, and a third layer composed of 128 sprites. VERA supports a single palette of 256 colours, freely chosen from the 4,096 possible colours available.

Audio

The VERA FPGA core produces audio output in i2S format, which is fed to the A/V port for conversion into an analog or digital format suitable for the target display device.

Audio is generated using a 16-voice stereo programmable sound generator, with each voice able to generate sounds independently, with the waveform for each chosen freely from among Pulse, Sawtooth, Triangle, and Noise.

VERA also generates sampled 48KHz 16-bit stereo audio from a 4KB on-chip memory buffer.

Interrupts

The VERA implementation in Sentinel 65X has a dedicated vectored interrupt line to the CPU, which can be triggered by any or all of four conditions: Sprite collision, line number, PCM buffer status, or VSYNC.

The Sentinel 65X A/V Port

Audio and video output in Sentinel 65X is directed to a pin header, which is connected to a small daughterboard which actually generates the final audio and video output signals, using electronics and connectors appropriate to the target display.

Pinout

The A/V port is a 24-pin female pin header, with a pin and row pitch of 2.54mm. The pinout of the port, as seen from above, is shown in the following table:

Pin	Label	Label	Pin
1	+3.3V	+5V	2
3	HSYNC	VSYNC	4
5	RGB_R0	RGB_R1	6
7	RGB_R2	RGB_R3	8
9	RGB_G0	RGB_G1	10
11	RGB_G2	RGB_G3	12
13	RGB_B0	RGB_B1	14
15	RGB_B2	RGB_B3	16
17	LRCK	BCK	18
19	ADATA	SYSCLK	20
21	SCL	SDA	22
23	GND	GND	24

VERA Memory

VERA implements 128KB of internal memory, which exists in its own independent address space, connected to the CPU's address space through address and data registers. This RAM's address space is numbered from 0x00000 to 0x1FFFF, and is organized as in the following table:

Address Range	Description
`0x00000` - `0x1F9BF`	Video RAM
`0x1F9C0` - `0x1F9FF`	Sound Registers
`0x1FA00` - `0x1FBFF`	Colour Palette
`0x1FC00` - `0x1FFFF`	Sprite Attributes

Hardware Registers

VERA is configured and controlled using a series of 32 memory-mapped I/O registers, located in the address space from 0x00DF00 to 0x00DF1F.

ADDRx_L

The ADDRx_L register is actually two registers, the ADDR0_L and ADDR1_L registers. Which of the two is accessed at memory address 0x00DF00 depends on the contents of ADDRSEL, which is bit 0 of the CTRL register, located at 0x00DF05.

The ADDR0_L and ADDR1_L registers control the low byte of the selected address in VERA memory for reading or writing with the DATA0 and DATA1 registers, located at 0x00DF03 and 0x00DF04 respectively.

ADDRx_M

The ADDRx_M register is actually two registers, the ADDR0_M and ADDR1_M registers. Which of the two is accessed at memory address 0x00DF01 depends on the contents of ADDRSEL, which is bit 0 of the CTRL register, located at 0x00DF05.

The ADDR0ML and ADDR1_M registers control the middle byte of the selected address in VERA memory for reading or writing with the DATA0 and DATA1 registers, located at 0x00DF03 and 0x00DF04 respectively.

ADDRx_H

The ADDRx_H register is actually two registers, the ADDR0_H and ADDR1_H registers. Which of the two is accessed at memory address 0x00DF00 depends on the contents of ADDRSEL, which is bit 0 of the CTRL register, located at 0x00DF05.

The ADDR0_H and ADDR1_H registers control the low byte of the selected address in VERA memory for reading or writing with the DATA0 and DATA1 registers, located at 0x00DF03 and 0x00DF04 respectively.

Bit 0 of the ADDRx_H is bit 16 of the address of the data port selected by ADDRSEL. Bits 1 and 2 of ADDRx_H are unused. Bit 3 is called DECR; when this bit is clear, the address of the selected data port will increment by the amount set with bits 4-7, called INCR, according to the table below. When DECR is set, then the address will decrement by the same amount.

`INCR` value	Address Increment
0	0
1	1
2	2
3	4
4	8
5	16
6	32
7	64
8	128
9	256
10	512
11	40
12	80
13	160
14	320
15	640

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