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Work on fleshing out sections
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@ -120,7 +120,11 @@ If the value in `INCR0` is nonzero, then after reading or writing from or to `DA
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### CTRL
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### CTRL
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The `CTRL` register, located at `0x00DF05`, contains three significant bits: bit 0, called `ADDRSEL`, determines which `DATAx` register the `ADDRx` registers refer to. Bit 1, called `DCSEL`, controls which set of registers are accessed at addresses `0x00DF09` through `0x00DF0C`. Bit 7, called `RESET`, will reset VERA to the initial power-on state when a `1` value is written to it.
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The `CTRL` register, located at `0x00DF05`, contains three significant bits:
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- Bit 0, called `ADDRSEL`, determines which `DATAx` register the `ADDRx` registers refer to.
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- Bit 1, called `DCSEL`, controls which set of registers are accessed at addresses `0x00DF09` through `0x00DF0C`.
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- Bit 7, called `RESET`, will reset VERA to the initial power-on state when a `1` value is written to it.
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### IEN
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### IEN
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@ -359,21 +363,25 @@ The bitmap address of a sprite is the top 12 bits of a 17-bit VERA memory addres
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The X and Y positions are 10-bit numbers representing the offset from the screen origin of the sprite's origin.
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The X and Y positions are 10-bit numbers representing the offset from the screen origin of the sprite's origin.
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`FIXME: How does the collision mask work?`
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The four-bit collision mask is used in detecting collisions between sprites in hardware. When two sprites' defined areas on screen overlap, their collision masks are used as operands in a binary AND operation; if the result is nonzero, then the collision will trigger a sprite collision interrupt if that interrupt source is enabled. Thus, a sprite with a collision mask of `0b0101` can trigger interrupts by colliding with sprites whose interrupt masks have bit 0, bit 2, or both set, regardless of the status of the other two bits. This makes sprite collision more efficient, by allowing groups of sprites which can and cannot detect collision with rach other to be defined, saving time resolving needless collisions.
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The layer position value determines the drawing order of the sprite relative to the two tile/bitmap layers:
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The layer position value determines the drawing order of the sprite relative to the two tile/bitmap layers:
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| Value | Description |
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| Value | Description |
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| :---: | :------------: |
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| :---: | :-----------------------------: |
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| 0 | Disabled |
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| 0 | Disabled |
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| 1 | Between background and layer 0 |
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| 1 | Between background and layer 0 |
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| 2 | Between layer 0 and 1 |
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| 2 | Between layer 0 and 1 |
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| 3 | Above layer 1 |
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| 3 | Above layer 1 |
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The horizontal and vertical flip bits, as you would expect, flip the sprite's bitmap along the horizontal and vertical axes, respectively.
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The horizontal and vertical flip bits, as you would expect, flip the sprite's bitmap along the horizontal and vertical axes, respectively.
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The palette offset is used to translate colour values from the sprite bitmap data, where those values are between 1 and 15. Such values are modified by adding the product of 16 and the palette offset.
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The palette offset is used to translate colour values from the sprite bitmap data, where those values are between 1 and 15. Such values are modified by adding the product of 16 and the palette offset.
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## Sprite Multiplexing
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While it should rarely be necessary, the presence of the raster line interrupt does allow for the re-use of sprites during the rendering of a single frame; the maximum number of effective sprites possible on screen in a single frame has not been experimentally demonstrated.
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## 16-Bit Reads/Writes
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## 16-Bit Reads/Writes
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With appropriate configuration of registers, it is possible to perform sequential 16-bit reads and writes to VERA address space:
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With appropriate configuration of registers, it is possible to perform sequential 16-bit reads and writes to VERA address space:
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