diff --git a/Audio & Video.md b/Audio & Video.md
index e27ebbe..30ac96e 100644
--- a/Audio & Video.md	
+++ b/Audio & Video.md	
@@ -15,9 +15,13 @@ The video generation is done using two independent tile/bitmap layers, and a thi
 
 ![12-bit RGB image of a parrot](images/RGB_12bits_palette_sample_image.png) ![12-bit colour palette](images/RGB_12bits_palette_color_test_chart.png)
 
+Each of the tile/bitmap layers is fully indepentent for content, mode, scrolling, etc. Both layers support two special modes useful for text displays, in 16 and 256 colours.
+
+There are enough sprites supported to act as a third bitmap layer, should the programmer wish to make use of sprites in that manner.
+
 ## Audio
 
-The VERA FPGA core produces audio output in i2S format, which is fed to the A/V port for conversion into an analog or digital format suitable for the target display device.
+The VERA FPGA core produces audio output in [I²S](https://en.wikipedia.org/wiki/I²S) format, which is fed to the A/V port for conversion into an analog or digital format suitable for the target display device.
 
 Audio is generated using a 16-voice stereo programmable sound generator, with each voice able to generate sounds independently, with the waveform for each  chosen freely from among Pulse, Sawtooth, Triangle, and Noise.
 
@@ -85,24 +89,24 @@ The `ADDR0_H` and `ADDR1_H` registers control the low byte of the selected addre
 
 Bit 0 of the `ADDRx_H` is bit 16 of the address of the data port selected by `ADDRSEL`. Bits 1 and 2 of `ADDRx_H` are unused. Bit 3 is called `DECR0` or `DECR1`; when this bit is clear, the address of the selected data port will increment by the amount set with bits 4-7, called `INCR0` or `INCR1`, according to the table below. When `DECR0` or `DECR1` is set, then the address will _decrement_ by the same amount when the matching data register is read from or written to.
 
-| `INCR` value   | Address Increment |
-| -------------: | ---------------: |
-|              0 |                0 |
-|              1 |                1 |
-|              2 |                2 |
-|              3 |                4 |
-|              4 |                8 |
-|              5 |               16 |
-|              6 |               32 |
-|              7 |               64 |
-|              8 |              128 |
-|              9 |              256 |
-|             10 |              512 |
-|             11 |               40 |
-|             12 |               80 |
-|             13 |              160 |
-|             14 |              320 |
-|             15 |              640 |
+| `INCR` value    | Address Increment |
+| :-------------: | :---------------: |
+|               0 |                 0 |
+|               1 |                 1 |
+|               2 |                 2 |
+|               3 |                 4 |
+|               4 |                 8 |
+|               5 |                16 |
+|               6 |                32 |
+|               7 |                64 |
+|               8 |               128 |
+|               9 |               256 |
+|              10 |               512 |
+|              11 |                40 |
+|              12 |                80 |
+|              13 |               160 |
+|              14 |               320 |
+|              15 |               640 |
 
 ### DATA0
 
@@ -366,6 +370,10 @@ The layer position value determines the drawing order of the sprite relative to
 | 2     | Between layer 0 and 1 |
 | 3     | Above layer 1  |
 
+The horizontal and vertical flip bits, as you would expect, flip the sprite's bitmap along the horizontal and vertical axes, respectively.
+
+The palette offset is used to translate colour values from the sprite bitmap data, where those values are between 1 and 15. Such values are modified by adding the product of 16 and the palette offset.
+
 ## 16-Bit Reads/Writes
 
 With appropriate configuration of registers, it is possible to perform sequential 16-bit reads and writes to VERA address space: