From a3e8329f044730a324eb60c9b477320df6633d00 Mon Sep 17 00:00:00 2001 From: Kyle Cardoza Date: Sun, 24 Mar 2024 00:57:12 -0400 Subject: [PATCH] Work on fleshing out sections --- Audio & Video.md | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Audio & Video.md b/Audio & Video.md index a451c90..10f8e43 100644 --- a/Audio & Video.md +++ b/Audio & Video.md @@ -209,6 +209,34 @@ Bits 4-5 encode the tile map width, while bits 6-7 encode the tile map height, a The `L0_MAPBASE` register, located at `0x00DF0DE`, encodes the high 8 bits of the 17-bit address in VERA memory where the map data for layer 0 can be found; since the bottom 9 bits are implicitly `0`, this means the map data must always begin on a 512-byte alignment boundary. +### L0_TILEBASE + +The `L0_TILEBASE` register, located at `0x00DF0F`, encodes the following data: + +- Bit 0 controls the pixel width of tiles in layer 0; a `0` value means that a tile is 8 pixels wide, while a `1` value means that tile is 16 pixels wide. +- Bit 1 controls the pixel height of tiles in layer 0; a `0` value means that a tile is 8 pixels tall, while a `1` value means that tile is 16 pixels tall. +- Bits 2-7 hold the top six bits of the 17-bit address in VERA memory where the tile data can be found; as bits 0-10 are implicitly `0`, this means that tile data is always aligned on a 2,048-byte boundary. + +### L0_HSCROLL_L / L0_HSCROLL_H + +The `L0_HSCROLL_L` and `L0_HSCROLL_H` registers, located at addresses `0x00DF10` and `0x00DF11`, encode the low order byte and high order 4 bits, respectively, of the layer 0 horizontal scroll value; this value ranges from 0 to 4,095, and is defined in terms of pixels. + +### L0_VSCROLL_L / L0_VSCROLL_H + +The `L0_VSCROLL_L` and `L0_VSCROLL_H` registers, located at addresses `0x00DF12` and `0x00DF13`, encode the low order byte and high order 4 bits, respectively, of the layer 0 vertical scroll value; this value ranges from 0 to 4,095, and is defined in terms of pixels. + +### Layer 1 Registers + +The layer 1 control registers function exactly as their equivalents for layer 0: + +- `L1_CONFIG` located at `0x00DF14` +- `L1_MAPBASE` located at `0x00DF15` +- `L1_TILEBASE` located at `0x00DF16` +- `L1_HSCROLL_L` located at `0x00DF17` +- `L1_HSCROLL_H` located at `0x00DF18` +- `L1_VSCROLL_L` located at `0x00DF19` +- `L1_VSCROLL_H` located at `0x00DF1A` + ## 16-Bit Reads/Writes With appropriate configuration of registers, it is possible to perform sequential 16-bit reads and writes to VERA address space: