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Work on fleshing out sections
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Kyle Cardoza
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Audio & Video.md
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Audio & Video.md
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@ -5,12 +5,30 @@ include_toc: true
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# Audio & Video
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# Audio & Video
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## VERA Video
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The VERA FPGA core, implemented on an iCE40 FPGA, is used to generate all audio and video signals produced by Sentinel 65X. This core, developed for the Commander X16 project by Frank van den Hoef, is licensed under the MIT license. It has been modified by Brian Swetland for Sentinel 65X, including porting it to be built using the Yosys open-source FPGA toolchain.
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## VERA Audio
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## Video
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The VERA video generator outputs a fixed 640x480, 60Hz digital RGB signal, with a total of 4,096 possible colours, using a 12-bit R4G4B4 colour space.
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The video generation is done using two independent tile/bitmap layers, and a third layer composed of 128 sprites. VERA supports a single palette of 256 colours, freely chosen from the 4,096 possible colours available.
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## Audio
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The VERA FPGA core produces audio output in i2S format, which is fed to the A/V port for conversion into an analog or digital format suitable for the target display device.
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Audio is generated using a 16-voice stereo programmable sound generator, with each voice able to generate sounds independently, with the waveform for each chosen freely from among Pulse, Sawtooth, Triangle, and Noise.
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VERA also generates sampled 48KHz 16-bit stereo audio from a 4KB on-chip memory buffer.
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## Interrupts
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The VERA implementation in Sentinel 65X has a dedicated vectored interrupt line to the CPU, which can be triggered by any or all of four conditions: Sprite collision, line number, PCM buffer status, or VSYNC.
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## The Sentinel 65X A/V Port
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## The Sentinel 65X A/V Port
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Audio and video output in Sentinel 65X is directed to a pin header, which is connected to a small daughterboard which actually generates the final audio and video output signals, using electronics and connectors appropriate to the target display.
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### Pinout
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### Pinout
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The A/V port is a 24-pin female pin header, with a pin and row pitch of 2.54mm. The pinout of the port, as seen from above, is shown in the following table:
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The A/V port is a 24-pin female pin header, with a pin and row pitch of 2.54mm. The pinout of the port, as seen from above, is shown in the following table:
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@ -29,3 +47,264 @@ The A/V port is a 24-pin female pin header, with a pin and row pitch of 2.54mm.
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| 19 | ADATA | | SYSCLK | 20 |
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| 19 | ADATA | | SYSCLK | 20 |
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| 21 | SCL | | SDA | 22 |
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| 21 | SCL | | SDA | 22 |
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| 23 | GND | | GND | 24 |
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| 23 | GND | | GND | 24 |
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## Hardware Registers
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VERA is configured and controlled using a series of 32 memory-mapped I/O registers, located in the address space from `0x00DF00` to `0x00DF1F`.
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<table>
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<tr>
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<th>Addr</th>
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<th>Name</th>
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<th>Bit 7</th>
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<th>Bit 6</th>
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<th>Bit 5 </th>
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<th>Bit 4</th>
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<th>Bit 3 </th>
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<th>Bit 2</th>
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<th>Bit 1 </th>
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<th>Bit 0</th>
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</tr>
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<tr>
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<td>$00</td>
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<td>ADDRx_L (x=ADDRSEL)</td>
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<td colspan="8" align="center">VRAM Address (7:0)</td>
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</tr>
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<tr>
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<td>$01</td>
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<td>ADDRx_M (x=ADDRSEL)</td>
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<td colspan="8" align="center">VRAM Address (15:8)</td>
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</tr>
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<tr>
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<td>$02</td>
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<td>ADDRx_H (x=ADDRSEL)</td>
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<td colspan="4" align="center">Address Increment</td>
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<td colspan="1" align="center">DECR</td>
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<td colspan="2" align="center">-</td>
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<td colspan="1" align="center">VRAM Address (16)</td>
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</tr>
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<tr>
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<td>$03</td>
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<td>DATA0</td>
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<td colspan="8" align="center">VRAM Data port 0</td>
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</tr>
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<tr>
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<td>$04</td>
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<td>DATA1</td>
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<td colspan="8" align="center">VRAM Data port 1</td>
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</tr>
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<tr>
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<td>$05</td>
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<td>CTRL</td>
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<td colspan="1" align="center">Reset</td>
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<td colspan="5" align="center">-</td>
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<td colspan="1" align="center">DCSEL</td>
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<td colspan="1" align="center">ADDRSEL</td>
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</tr>
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<tr>
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<td>$06</td>
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<td>IEN</td>
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<td colspan="1" align="center">IRQ Line (8)</td>
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<td colspan="1" align="center">Scan Line (8)</td>
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<td colspan="2" align="center">-</td>
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<td colspan="1" align="center">AFLOW</td>
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<td colspan="1" align="center">SPRCOL</td>
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<td colspan="1" align="center">LINE</td>
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<td colspan="1" align="center">VSYNC</td>
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</tr>
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<tr>
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<td>$07</td>
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<td>ISR</td>
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<td colspan="4" align="center">Sprite collissions</td>
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<td colspan="1" align="center">AFLOW</td>
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<td colspan="1" align="center">SPRCOL</td>
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<td colspan="1" align="center">LINE</td>
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<td colspan="1" align="center">VSYNC</td>
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</tr>
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<tr>
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<td>$08</td>
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<td>IRQLINE_L (Write only)</td>
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<td colspan="8" align="center">IRQ line (7:0)</td>
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</tr>
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<tr>
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<td>$08</td>
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<td>SCANLINE_L (Read only)</td>
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<td colspan="8" align="center">Scan line (7:0)</td>
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</tr>
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<tr>
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<td>$09</td>
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<td>DC_VIDEO (DCSEL=0)</td>
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<td colspan="1" align="center">Current Field</td>
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<td colspan="1" align="center">Sprites Enable</td>
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<td colspan="1" align="center">Layer1 Enable</td>
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<td colspan="1" align="center">Layer0 Enable</td>
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<td colspan="1" align="center">-</td>
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<td colspan="1" align="center">Chroma Disable</td>
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<td colspan="2" align="center">Output Mode</td>
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</tr>
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<tr>
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<td>$0A</td>
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<td>DC_HSCALE (DCSEL=0)</td>
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<td colspan="8" align="center">Active Display H-Scale</td>
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</tr>
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<tr>
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<td>$0B</td>
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<td>DC_VSCALE (DCSEL=0)</td>
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<td colspan="8" align="center">Active Display V-Scale</td>
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</tr>
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<tr>
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<td>$0C</td>
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<td>DC_BORDER (DCSEL=0)</td>
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<td colspan="8" align="center">Border Color</td>
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</tr>
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<tr>
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<td>$09</td>
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<td>DC_HSTART (DCSEL=1)</td>
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<td colspan="8" align="center">Active Display H-Start (9:2)</td>
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</tr>
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<tr>
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<td>$0A</td>
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<td>DC_HSTOP (DCSEL=1)</td>
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<td colspan="8" align="center">Active Display H-Stop (9:2)</td>
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</tr>
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<tr>
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<td>$0B</td>
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<td>DC_VSTART (DCSEL=1)</td>
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<td colspan="8" align="center">Active Display V-Start (8:1)</td>
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</tr>
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<tr>
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<td>$0C</td>
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<td>DC_VSTOP (DCSEL=1)</td>
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<td colspan="8" align="center">Active Display V-Stop (8:1)</td>
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</tr>
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<tr>
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<td>$0D</td>
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<td>L0_CONFIG</td>
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<td colspan="2" align="center">Map Height</td>
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<td colspan="2" align="center">Map Width</td>
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<td colspan="1" align="center">T256C</td>
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<td colspan="1" align="center">Bitmap Mode</td>
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<td colspan="2" align="center">Color Depth</td>
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</tr>
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<tr>
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<td>$0E</td>
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<td>L0_MAPBASE</td>
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<td colspan="8" align="center">Map Base Address (16:9)</td>
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</tr>
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<tr>
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<td>$0F</td>
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<td>L0_TILEBASE</td>
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<td colspan="6" align="center">Tile Base Address (16:11)</td>
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<td colspan="1" align="center">Tile Height</td>
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<td colspan="1" align="center">Tile Width</td>
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</tr>
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<tr>
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<td>$10</td>
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<td>L0_HSCROLL_L</td>
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<td colspan="8" align="center">H-Scroll (7:0)</td>
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</tr>
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<tr>
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<td>$11</td>
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<td>L0_HSCROLL_H</td>
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<td colspan="4" align="center">-</td>
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<td colspan="8" align="center">H-Scroll (11:8)</td>
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</tr>
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<tr>
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<td>$12</td>
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<td>L0_VSCROLL_L</td>
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<td colspan="8" align="center">V-Scroll (7:0)</td>
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</tr>
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<tr>
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<td>$13</td>
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<td>L0_VSCROLL_H</td>
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<td colspan="4" align="center">-</td>
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<td colspan="8" align="center">V-Scroll (11:8)</td>
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</tr>
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<tr>
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<td>$14</td>
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<td>L1_CONFIG</td>
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<td colspan="2" align="center">Map Height</td>
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<td colspan="2" align="center">Map Width</td>
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<td colspan="1" align="center">T256C</td>
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<td colspan="1" align="center">Bitmap Mode</td>
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<td colspan="2" align="center">Color Depth</td>
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</tr>
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<tr>
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<td>$15</td>
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<td>L1_MAPBASE</td>
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<td colspan="8" align="center">Map Base Address (16:9)</td>
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</tr>
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<tr>
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<td>$16</td>
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<td>L1_TILEBASE</td>
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<td colspan="6" align="center">Tile Base Address (16:11)</td>
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<td colspan="1" align="center">Tile Height</td>
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<td colspan="1" align="center">Tile Width</td>
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</tr>
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<tr>
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<td>$17</td>
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<td>L1_HSCROLL_L</td>
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<td colspan="8" align="center">H-Scroll (7:0)</td>
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</tr>
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<tr>
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<td>$18</td>
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<td>L1_HSCROLL_H</td>
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<td colspan="4" align="center">-</td>
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<td colspan="8" align="center">H-Scroll (11:8)</td>
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</tr>
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<tr>
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<td>$19</td>
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<td>L1_VSCROLL_L</td>
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<td colspan="8" align="center">V-Scroll (7:0)</td>
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</tr>
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<tr>
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<td>$1A</td>
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<td>L1_VSCROLL_H</td>
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<td colspan="4" align="center">-</td>
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<td colspan="8" align="center">V-Scroll (11:8)</td>
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</tr>
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<tr>
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<td>$1B</td>
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<td>AUDIO_CTRL</td>
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<td colspan="1" align="center">FIFO Full / FIFO Reset</td>
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<td colspan="1" align="center">FIFO Empty</td>
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<td colspan="1" align="center">16-Bit</td>
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<td colspan="1" align="center">Stereo</td>
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<td colspan="4" align="center">PCM Volume</td>
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</tr>
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<tr>
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<td>$1C</td>
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<td>AUDIO_RATE</td>
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<td colspan="8" align="center">PCM Sample Rate</td>
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</tr>
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<tr>
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<td>$1D</td>
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<td>AUDIO_DATA</td>
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<td colspan="8" align="center">Audio FIFO data (write-only)</td>
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</tr>
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<tr>
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<td>$1E</td>
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<td>SPI_DATA</td>
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<td colspan="8" align="center">Data</td>
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</tr>
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<tr>
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<td>$1F</td>
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<td>SPI_CTRL</td>
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<td colspan="1" align="center">Busy</td>
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<td colspan="4" align="center">-</td>
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<td colspan="1" align="center">Auto-tx</td>
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<td colspan="1" align="center">Slow clock</td>
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<td colspan="1" align="center">Select</td>
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</tr>
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</table>
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## VERA Memory
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VERA implements 128KB of internal memory, which exists in its own independent address space, connected to the CPU's address space through address and data registers. This RAM's address space is numbered from `0x00000` to `0x1FFFF`, and is organized as in the following table:
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| Address Range | Description |
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| :-------------------: | :---------------: |
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| `0x00000` - `0x1F9BF` | Video RAM |
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| `0x1F9C0` - `0x1F9FF` | Sound Registers |
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| `0x1FA00` - `0x1FBFF` | Colour Palette |
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| `0x1FC00` - `0x1FFFF` | Sprite Attributes |
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@ -24,3 +24,5 @@ This enables the binary loader to be extremely simple, as the data to be read in
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The final segment is special: its target address represents the entry point to the executable, and its length of data value is always `0x000000`. The loader can easily detect this to identify when loading is done and where to enter the program.
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The final segment is special: its target address represents the entry point to the executable, and its length of data value is always `0x000000`. The loader can easily detect this to identify when loading is done and where to enter the program.
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The Sentinel 65X SDK will be configured to produce PGZ format executables by default, with the option to instead export to a file suitable for writing to a ROM cartridge.
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The Sentinel 65X SDK will be configured to produce PGZ format executables by default, with the option to instead export to a file suitable for writing to a ROM cartridge.
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Note: The open-source 64Tass assembler is also capable of generating PGZ-format executables.
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Reference in New Issue