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Sentinel65X-Handbook
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Work on fleshing out sections

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Kyle Cardoza 2024-03-24 01:35:45 -04:00
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@ -290,6 +290,8 @@ The palette is stored in VERA memory beginning at VERA address `0x1FA00`, and co
| 0 | G3 | G2 | G1 | G0 | B3 | B2 | B1 | B0 |
| 1 | | | | | R3 | R2 | R1 | R0 |
Note that the high order four bits in the second byte of each palette entry is unused.
## 16-Bit Reads/Writes
With appropriate configuration of registers, it is possible to perform sequential 16-bit reads and writes to VERA address space:
@ -303,4 +305,4 @@ With appropriate configuration of registers, it is possible to perform sequentia
Such 16-bit reads and writes are almost twice as cycle-efficient as reading or writing in 8-bit increments, as the extra byte takes only a single extra CPU cycle.
The SDK will provide a C function pair `vera_memcpy_read()` and `vera_memcpu_write()` handle bulk data transfers; it will use this mode of reading and writing without futher intervention by the programmer.
The SDK will provide a C function pair `vera_memcpy_read()` and `vera_memcpy_write()` handle bulk data transfers; it will use this mode of reading and writing without futher intervention by the programmer.