Work on fleshing out sections

Audio & Video.md

@@ -382,6 +382,33 @@ The palette offset is used to translate colour values from the sprite bitmap dat
 
 While it should rarely be necessary, the presence of the raster line interrupt does allow for the re-use of sprites during the rendering of a single frame; the maximum number of effective sprites possible on screen in a single frame has not been experimentally demonstrated.
 
+## Tile Data
+
+The individual tile bitmaps are 8x8, 8x16, 16x8, or 16x16 pixel bitmaps, which can be in a 1, 2, 4, or 8bpp format, with each pixel stored as a colour palette index.
+
+## Map Data
+
+Tilemaps are stored as sequences of two-byte structures. The interpretation of those bytes depends on the settings of the layer.
+
+### 1BPP Tile Mode
+
+In 1bpp tile mode, with the `T256C` flag cleared, the first byte of the map data is an index into the tile data, and the second byte is split into two nybbles, the low-order nybble holding the foreground colour, and the high-order nybble holding the background colour for that tile.
+
+In 1bpp tile mode with the `T256C` flag set, instead the second byte is the foreground colour of the tile, with the background colour being transparent.
+
+### 2/4/8BPP Tile Mode
+
+In other bit depths, tile mode interprets the first byte of the map data is the low-order eight bits of the tile index. The second byte is interpreted as follows:
+
+- The low two bits of the second byte are the high-order bits of the tile index.
+- Bits 2 and 4 control horizontal and vertical flipping of the bimap used for that position in the map.
+- Bits 4-7 contain a 4-bit palette offset.
+
+Palette offsets modify the colour indices in the tile data as follows:
+
+- Color 0 (transparent) and 16-255 are used as-is
+- Colours 1-15 are modified by adding the product of the palette offset and 16 -- that is, if the palette offset is 2, then colours 1-15 will have 32 added to the palette index.
+
 ## 16-Bit Reads/Writes
 
 With appropriate configuration of registers, it is possible to perform sequential 16-bit reads and writes to VERA address space: