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Sentinel65X-Handbook
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Work on fleshing out sections

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Kyle Cardoza 2024-03-23 20:50:14 -04:00
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Audio & Video.md
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@ -48,10 +48,6 @@ The A/V port is a 24-pin female pin header, with a pin and row pitch of 2.54mm.
| 21 | SCL | | SDA | 22 | | 21 | SCL | | SDA | 22 |
| 23 | GND | | GND | 24 | | 23 | GND | | GND | 24 |
## Hardware Registers
VERA is configured and controlled using a series of 32 memory-mapped I/O registers, located in the address space from `0x00DF00` to `0x00DF1F`.
## VERA Memory ## VERA Memory
VERA implements 128KB of internal memory, which exists in its own independent address space, connected to the CPU's address space through address and data registers. This RAM's address space is numbered from `0x00000` to `0x1FFFF`, and is organized as in the following table: VERA implements 128KB of internal memory, which exists in its own independent address space, connected to the CPU's address space through address and data registers. This RAM's address space is numbered from `0x00000` to `0x1FFFF`, and is organized as in the following table:
@ -62,3 +58,13 @@ VERA implements 128KB of internal memory, which exists in its own independent ad
| `0x1F9C0` - `0x1F9FF` | Sound Registers | | `0x1F9C0` - `0x1F9FF` | Sound Registers |
| `0x1FA00` - `0x1FBFF` | Colour Palette | | `0x1FA00` - `0x1FBFF` | Colour Palette |
| `0x1FC00` - `0x1FFFF` | Sprite Attributes | | `0x1FC00` - `0x1FFFF` | Sprite Attributes |
## Hardware Registers
VERA is configured and controlled using a series of 32 memory-mapped I/O registers, located in the address space from `0x00DF00` to `0x00DF1F`.
### ADDRx_L
| `0x00DF00` | ||
| :--------: | :---: ||
| VRAM Address (Low Byte ) ||