forked from rebecca/BSX
106 lines
7.3 KiB
Org Mode
106 lines
7.3 KiB
Org Mode
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* I/O is at $00:df00 - $00:dfff, and is always mapped in.
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*note* Any RAM that might also be mapped to this range is ignored.
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* ROM0 logic
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ROM0 low if CS4 XOR CS7 low.
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* Booted Memory Map
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$00:0000-$00:deff : SRAM
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-- *todo* where will direct page & stack be? --
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$00:df00-$00:dfff : I/O
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$df00-$00:df1f : VERA
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$df20 : PD4 (data register, port 4)
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$df21 : PD5 (data register, port 5)
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$df22 : PD6 (data register, port 6)
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$df23 : PD7 (data register, port 7)
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$df24 : PDD4 (direction register, port 4)
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$df25 : PDD5 (direction register, port 5)
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$df26 : PDD6 (direction register, port 6)
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$df27 : PCS7 (port 7 chip select)
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| --- | ---- | ----------------- | ---------- | ----------------------------------------------------------------------- |
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| bit | name | address | booted val | notes |
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| --- | ---- | ----------------- | ---------- | ----------------------------------------------------------------------- |
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| 7 | CS7 | $c0:0000-$ff:ffff | 1 | Used with CS4 to generate ROM0 |
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| 6 | CS6 | $40:0000-$bf:ffff | 1 | Wired to cartridge and expansion ports. |
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| 5 | CS5 | $00:0000-$3f:ffff | 1 | Enables SRAM |
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| 4 | CS4 | $00:8000-$00:ffff | 0 | Used during boot, disabled afterwards. Used with CS7 to generate ROM0. |
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| 3 | CS3 | | 0 | Used as GPIO (which port?) |
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| 2 | CS2 | | 0 | Used as GPIO (which port?) |
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| 1 | CS1 | $00:dfc0-$00:dfff | 1 | 0 = PIB SRAM, 1 = Clock Port |
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| 0 | CS0 | $00:df00-$00:df1f | 1 | 0 = GPIO control, 1 = VERA |
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| --- | ---- | ----------------- | ---------- | ----------------------------------------------------------------------- |
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$df28-df3f : unused / reserved
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$df40 : BCR (bus control register)
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bit 0: 0: address & data pins are GPIO
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1: address & data pins are buses.
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*note* we always have this set to 1.
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$df41 : SSCR (system speed control register)
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$df42 : TCR (timer control register)
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$df43 : TER (timer enable register)
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$df44 : TIFR (timer interrupt flag register)
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$df45 : EIFR (edge interrupt enable register)
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$df46 : TIER (timer interrupt enable register)
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$df47 : EIER (edge interrupt enable register)
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$df48 : UIFR (UART interrupt flag register)
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$df49 : UIER (UART interrupt enable register)
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$df4a-df4f : unused / reserved
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[$df50-df6f : timer register memory map]
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$df5a : T5LL (Timer 5 Latch Low)
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$df5b : T5LH (Timer 5 Latch High)
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$df6a : T5CL (Timer 5 Counter Low)
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$df6b : T5CH (Timer 5 Counter High)
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[$df70-dfbf : Communication Registers (2.5.1)]
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*todo* not sure what we use from here yet.
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$dfc0-dfff : Clock Port (64 bytes)
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$00:e000-$00:ffff : SRAM
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$01:0000-$3f:ffff : SRAM
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$04:0000-$bf:ffff : Cartridge & Expansion
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$c0:0000-$ff:ffff : ROM
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* timers & special IRQs
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*todo* irne64 - !VIRQ
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*todo* irqt5
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* cpu pins to signals note: !xyz should be interpreted as xyz with overline
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| ---- | ---------- | -------------- | -------------- | ----------- | ----------- | ------------- | ----------- |
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| pin# | pin name | signal (I/O) | control bit | signal cb 0 | signal cb 1 | direction reg | data reg |
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| ---- | ---------- | -------------- | -------------- | ----------- | ----------- | ------------- | ----------- |
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| 5 | p4.5 (P45) | MISO (I) | PIBER0 | P45 | PIRS0 | PDD4 $df24:5 | PD4 $df20:5 |
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| 6 | p4.6 (P46) | SD_CD (I) | PIBER0 | P46 | PIRS1 | PDD4 $df24:6 | PD4 $df20:6 |
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| 7 | p4.7 (P47) | SD_WP (I) | PIBER0 | P47 | PIRS2 | PDD4 $df24:7 | PD4 $df20:7 |
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| 8 | p5.0 (P50) | SNES_CLK (O) | PIBER0 | P50 | PID0 | PDD5 $df25:0 | PD5 $df21:0 |
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| 9 | p5.1 (P51) | SNES_LATCH (O) | PIBER0 | P51 | PID1 | PDD5 $df25:1 | PD5 $df21:1 |
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| 10 | p5.2 (P52) | SNES_DATA0 (I) | PIBER0 | P52 | PID2 | PDD5 $df25:2 | PD5 $df21:2 |
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| 11 | p5.3 (P53) | SNES_DATA1 (I) | PIBER0 | P53 | PID3 | PDD5 $df25:3 | PD5 $df21:3 |
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| 12 | p5.4 (P54) | SNES_DATA2 (I) | PIBER0 | P54 | PID4 | PDD5 $df25:4 | PD5 $df21:4 |
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| 13 | p5.5 (P55) | SNES_DATA3 (I) | PIBER0 | P55 | PID5 | PDD5 $df25:5 | PD5 $df21:5 |
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| 22 | p6.4 (P64) | !VIRQ (I) | ACSR25 | P64 | RXD2 | PDD6 $df26:4 | PD6 $df22:6 |
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| 72 | !CS0 (P70) | !I/O0 (O) | PCS70 | P70 | CS0B | PCS7 $df27:0 | PD7 $df23:0 |
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| 73 | !CS1 (P71) | !I/O1 (O) | PCS71 | P71 | CS1B | PCS7 $df27:1 | PD7 $df23:1 |
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| 74 | p7.2 (P72) | !FLASH_SS (O) | PCS72 | P72 | CS2B | PCS7 $df27:2 | PD7 $df23:2 |
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| 75 | p7.3 (P73) | SCK (O) | PCS73 | P73 | CS3B | PCS7 $df27:3 | PD7 $df23:3 |
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| 80 | !CS4 (P74) | !CS4 (O) | PCS74 | P74 | CS4B | PCS7 $df27:4 | PD7 $df23:4 |
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| 81 | !CS5 (P75) | !CS5 (O) | PCS75 | P75 | CS5B | PCS7 $df27:5 | PD7 $df23:5 |
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| 82 | !CS6 (P76) | !CS6 (O) | PCS76 | P76 | CS6B | PCS7 $df27:6 | PD7 $df23:6 |
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| 83 | !CS7 (P77) | !CS7 (O) | PCS77 | P77 | CS7B | PCS7 $df27:7 | PD7 $df23:7 |
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| 94 | TG0 (TG0) | TG0 (O) | TCR31 | n/a | TG0 | n/a | n/a |
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| 95 | TG1 (TG1) | TG1 (O) | TCR33 | n/a | TG1 | n/a | n/a |
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| 98 | p4.2 (P42) | !FPGA_RES (O) | PIBER0 | P42 | PIIB | PDD4 $df24:2 | PD4 $df20:2 |
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| 99 | p4.3 (P43) | CDONE (I+O) | PIBER0*PIBER1B | P43 | PIWEB | PDD4 $df24:3 | PD4 $df20:3 |
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| 100 | p4.4 (P44) | MOSI (O) | PIBER0*PIBER1B | P44 | PIRS0 | PDD4 $df24:4 | PD4 $df20:4 |
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| ---- | ---------- | -------------- | -------------- | ----------- | ----------- | ------------- | ----------- |
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* How to read/write a signal?
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So MISO (in the current prototype) is set to P4.5, that is, bit five of port 4. So since MISO is an input,
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you would set bit five of PDD4 (port 4 data direction) to zero; then bit five of PD4 (port 4 data) will always
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read the current value of that input line. [see 2.5.4 I/O Register Memory Map] I'm not sure the cb names are helpful.
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TG0 and TG1 are not usable this way; they are only available to the tone generator, which uses an internal timer
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to produce a sine wave on either or both.
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SCK is currently wired to P7.2; this is a pin shared with /CS2, which is unused. We set PCS7 bit 2 to zero, and then
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the state of bit 2 of PD7 will always be reflected on the pin (there is no PDD7, as port 7 is always an output).
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I/00 is a renamed /CS0, and goes low whenever memory from 0x00DF000 to 00x00DF1F is accessed as long as bit zero of PCS7
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is high.
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