29 lines
1.0 KiB
Plaintext
29 lines
1.0 KiB
Plaintext
BLOCK RESETPATHS;
|
|
BLOCK ASYNCPATHS;
|
|
|
|
SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 MASTER_SPI_PORT=ENABLE SLAVE_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE;
|
|
|
|
LOCATE COMP "CLK" SITE "G2";
|
|
IOBUF PORT "CLK" PULLMODE=NONE IO_TYPE=LVCMOS33;
|
|
FREQUENCY PORT "CLK" 25 MHZ;
|
|
|
|
## LED indicators "blinkey" and "gpio" sheet
|
|
LOCATE COMP "paint" SITE "H3";
|
|
LOCATE COMP "hsync" SITE "E1";
|
|
LOCATE COMP "vsync" SITE "E2";
|
|
IOBUF PORT "paint" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
IOBUF PORT "hsync" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
IOBUF PORT "vsync" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
|
|
LOCATE COMP "RST_N" SITE "D6"; # BTN_PWRn (inverted logic)
|
|
IOBUF PORT "RST_N" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
|
|
LOCATE COMP "uart_rx_v" SITE "M1"; # FIRE1
|
|
IOBUF PORT "uart_rx_v" PULLMODE=UP IO_TYPE=LVCMOS33;
|
|
|
|
LOCATE COMP "uart_tx" SITE "L4"; # FPGA transmits to ftdi
|
|
IOBUF PORT "uart_tx" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
|
|
LOCATE COMP "wifi_gpio0" SITE "L2";
|
|
IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|