218 lines
7.3 KiB
Plaintext
218 lines
7.3 KiB
Plaintext
package VRAMCore;
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import Connectable::*;
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import GetPut::*;
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import ClientServer::*;
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import DReg::*;
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import BRAM::*;
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import Vector::*;
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import FIFOF::*;
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import SpecialFIFOs::*;
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import Real::*;
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import Printf::*;
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import DelayLine::*;
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import ECP5_RAM::*;
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export VRAMAddr;
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export VRAMData;
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export VRAMRequest;
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export VRAMResponse;
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export VRAMClient;
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export VRAMServer;
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export VRAMCore;
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export mkVRAMCore;
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typedef Bit#(8) VRAMData;
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// Each byte RAM we build below can address 4096 bytes, which is 12
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// address bits.
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typedef UInt#(12) ByteAddr;
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typedef UInt#(3) ChipAddr;
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// ByteRAM is two EBRs glued together to make a whole-byte memory.
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typedef EBR#(ByteAddr, VRAMData, ByteAddr, VRAMData) ByteRAM;
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// mkByteRAM glues two ECP5 EBRs together to make a 4096x8b memory
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// block. Like the underlying ECP5 EBRs, callers must bring their own
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// flow control to read out responses one cycle after putting a read
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// request.
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module mkByteRAM(ChipAddr chip_addr, ByteRAM ifc);
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EBRPortConfig cfg = defaultValue;
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cfg.chip_select_addr = chip_addr;
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EBR#(ByteAddr, Bit#(4), ByteAddr, Bit#(4)) upper <- mkEBRCore(cfg, cfg);
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EBR#(ByteAddr, Bit#(4), ByteAddr, Bit#(4)) lower <- mkEBRCore(cfg, cfg);
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interface EBRPort portA;
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method Action put(ChipAddr chip_select, Bool write, ByteAddr addr, VRAMData data_in);
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upper.portA.put(chip_select, write, addr, truncate(data_in>>4));
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lower.portA.put(chip_select, write, addr, truncate(data_in));
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endmethod
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method VRAMData read();
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return (extend(upper.portA.read())<<4) | (extend(lower.portA.read()));
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endmethod
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endinterface
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interface EBRPort portB;
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method Action put(ChipAddr chip_select, Bool write, ByteAddr addr, VRAMData data_in);
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upper.portB.put(chip_select, write, addr, truncate(data_in>>4));
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lower.portB.put(chip_select, write, addr, truncate(data_in));
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endmethod
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method VRAMData read();
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return (extend(upper.portB.read())<<4) | (extend(lower.portB.read()));
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endmethod
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endinterface
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endmodule : mkByteRAM
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// mkByteRAMArray arrays up to 8 mkByteRAMs together, using the
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// hardwired chip select lines to route inputs appropriately and a mux
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// tree to collect outputs. With num_chips=8, the resulting ByteRAM is
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// 32768x8b.
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module mkByteRAMArray(Integer num_chips, ByteRAM ifc);
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if (num_chips > 8)
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error("mkByteRAMArray can only array 8 raw ByteRAMs");
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ByteRAM blocks[num_chips];
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for (Integer i=0; i<num_chips; i=i+1)
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blocks[i] <- mkByteRAM(fromInteger(i));
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DelayLine#(ChipAddr) read_chip_A <- mkDelayLine(1);
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DelayLine#(ChipAddr) read_chip_B <- mkDelayLine(1);
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interface EBRPort portA;
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method Action put(ChipAddr chip_select, Bool write, ByteAddr addr, VRAMData data_in);
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for (Integer i=0; i<num_chips; i=i+1)
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blocks[i].portA.put(chip_select, write, addr, data_in);
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if (write)
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read_chip_A <= chip_select;
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endmethod
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method VRAMData read();
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if (read_chip_A.ready)
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if (read_chip_A <= fromInteger(num_chips-1))
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return blocks[read_chip_A].portA.read();
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else
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return 0;
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else
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return 0;
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endmethod
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endinterface
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interface EBRPort portB;
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method Action put(ChipAddr chip_select, Bool write, ByteAddr addr, VRAMData data_in);
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for (Integer i=0; i<num_chips; i=i+1)
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blocks[i].portB.put(chip_select, write, addr, data_in);
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if (write)
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read_chip_B <= chip_select;
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endmethod
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method VRAMData read();
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if (read_chip_B.ready)
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if (read_chip_B <= fromInteger(num_chips-1))
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return blocks[read_chip_B].portB.read();
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else
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return 0;
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else
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return 0;
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endmethod
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endinterface
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endmodule
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typedef UInt#(2) ArrayAddr;
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typedef UInt#(17) VRAMAddr;
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typedef struct {
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VRAMAddr addr;
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Maybe#(VRAMData) data;
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} VRAMRequest deriving (Bits, Eq);
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typedef struct {
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VRAMData data;
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} VRAMResponse deriving (Bits, Eq);
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typedef Server#(VRAMRequest, VRAMResponse) VRAMServer;
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typedef Client#(VRAMRequest, VRAMResponse) VRAMClient;
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interface VRAMCore;
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interface VRAMServer portA;
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interface VRAMServer portB;
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endinterface
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// mkVRAMCore creates a dual port VRAM of the specified size, using
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// ECP5 EBR memory primitives. The memory size must be a multiple of
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// 4KiB, with a maximum of 128KiB.
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//
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// The returned VRAMCore servers implement flow control. As long as
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// responses are processed as soon as they're available, each port can
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// process one memory operation per cycle.
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//
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// The VRAMCore does not prevent write-write or write-read conflicts
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// between the ports. The outcome of a simultaneous write to the same
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// address is unspecified, as is the read output in a simultaneous
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// read and write of the same address. The caller must use external
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// arbitration to avoid such accesses.
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module mkVRAMCore(Integer num_kilobytes, VRAMCore ifc);
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if (num_kilobytes > 128)
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error("maximum VRAMCore size is 128KiB");
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let num_bytes = num_kilobytes*1024;
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if (num_bytes % 4096 != 0)
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error("VRAMCore must be a multiple of 4096b");
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let num_byterams = num_bytes/4096;
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let num_arrays = ceil(fromInteger(num_byterams) / 8);
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function Tuple3#(ArrayAddr, ChipAddr, ByteAddr) split_addr(VRAMAddr a);
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if (num_bytes < 128*1024)
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a = a % fromInteger(num_bytes);
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match {.top, .byteaddr} = split(pack(a));
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Tuple2#(Bit#(SizeOf#(ArrayAddr)), Bit#(SizeOf#(ChipAddr))) route = split(top);
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return tuple3(unpack(tpl_1(route)), unpack(tpl_2(route)), unpack(byteaddr));
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endfunction
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ByteRAM arrays[num_arrays];
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for (Integer i=0; i<num_arrays; i=i+1) begin
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let array_size = min(num_byterams - (i*8), 8);
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arrays[i] <- mkByteRAMArray(array_size);
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end
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Reg#(Maybe#(ArrayAddr)) inflight_A[2] <- mkCReg(2, tagged Invalid);
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Reg#(Maybe#(ArrayAddr)) inflight_B[2] <- mkCReg(2, tagged Invalid);
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interface VRAMServer portA;
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interface Put request;
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method Action put(VRAMRequest req) if (inflight_A[1] matches tagged Invalid);
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match {.array, .chip, .byteaddr} = split_addr(req.addr);
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arrays[array].portA.put(chip, isValid(req.data), byteaddr, fromMaybe(0, req.data));
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if (!isValid(req.data))
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inflight_A[1] <= tagged Valid array;
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endmethod
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endinterface
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interface Get response;
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method ActionValue#(VRAMResponse) get() if (inflight_A[0] matches tagged Valid .array);
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inflight_A[0] <= tagged Invalid;
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return VRAMResponse{data: arrays[array].portA.read()};
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endmethod
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endinterface
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endinterface
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interface VRAMServer portB;
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interface Put request;
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method Action put(VRAMRequest req) if (inflight_B[1] matches tagged Invalid);
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match {.array, .chip, .byteaddr} = split_addr(req.addr);
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arrays[array].portB.put(0, isValid(req.data), byteaddr, fromMaybe(0, req.data));
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if (!isValid(req.data))
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inflight_B[1] <= tagged Valid array;
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endmethod
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endinterface
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interface Get response;
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method ActionValue#(VRAMResponse) get() if (inflight_B[0] matches tagged Valid .array);
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inflight_B[0] <= tagged Invalid;
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return VRAMResponse{data: arrays[array].portB.read()};
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endmethod
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endinterface
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endinterface
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endmodule
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endpackage
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