200 lines
7.5 KiB
Python
200 lines
7.5 KiB
Python
#!/usr/bin/env python
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import os.path
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from pathlib import Path
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from invoke import task
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from textwrap import dedent
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import shutil
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def ensure_build_dirs(root : Path, *subdirs : list[Path]):
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if root.is_file():
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root = root.parent / root.stem
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ret = []
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for d in subdirs:
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out = "out" / root / d
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out.mkdir(mode=0o750, parents=True, exist_ok=True)
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ret.append(out)
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return ret
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def bsc_root(c):
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out = c.run("bsc --help", hide="both")
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for l in out.stdout.splitlines():
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dir_prefix = "Bluespec directory: "
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if l.startswith(dir_prefix):
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return Path(l[len(dir_prefix):])
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raise RuntimeError("Couldn't locate Bluespec root dir")
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def find_verilog_modules(c, modules):
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libpaths = [Path("lib"), bsc_root(c) / "Verilog"]
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ret = []
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for module in modules:
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module_path = None
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for p in libpaths:
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f = p / Path(module).with_suffix(".v")
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if f.is_file():
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module_path = f
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break
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if module_path is None:
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raise RuntimeError(f"Cannot find verilog module {module} in {libpaths}")
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ret.append(module_path)
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return ret
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def print_filtered_paragraphs(s, *paragraph_prefixes, common_prefix=""):
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for block in s.split("\n\n"):
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for p in paragraph_prefixes:
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if block.removeprefix(common_prefix).startswith(p):
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print('\n'.join(s.removeprefix(common_prefix) for s in block.splitlines()))
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print("")
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def expand_build_target(target):
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t = Path(target)
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if t.is_dir():
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yield from t.glob("**/*.bsv")
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elif t.is_file() and t.suffix == ".bsv":
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yield t
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else:
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raise ValueError(f"Unknown target type {t}")
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def resolve_synth_target(target):
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target = Path(target)
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if '/' not in str(target):
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target = "hardware" / target
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if target.is_dir():
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target /= "Top.bsv"
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if not target.is_file():
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raise ValueError(f"Unknown target type {target}")
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return target
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def expand_test_target(target):
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t = Path(target)
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if t.is_dir():
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yield from t.glob("**/*_Test.bsv")
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elif t.is_file() and t.name.endswith("_Test.bsv"):
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yield t
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else:
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raise ValueError(f"Unknown target type {t}")
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def phase(name):
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print("")
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print("*"*(len(name)+6))
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print(f"** {name} **")
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print("*"*(len(name)+6))
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print("")
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@task
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def build(c, target="."):
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phase("Compile Bluespec")
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verilog_files = []
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for target in expand_build_target(target):
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out_info, out_verilog, out_bsc = ensure_build_dirs(target, "info", "verilog", "bsc")
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print(f"Building {target}")
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c.run(f"bsc -aggressive-conditions -check-assert -remove-dollar -remove-empty-rules -remove-false-rules -remove-starved-rules -remove-unused-modules -show-method-conf -show-method-bvi -u -verilog -info-dir {out_info} -vdir {out_verilog} -bdir {out_bsc} -p {target.parent}:vram:lib:%/Libraries -show-module-use -show-compiles {target}")
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module_name = Path(f"mk{target.stem}")
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verilog_main_file = out_verilog / module_name.with_suffix(".v")
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if verilog_main_file.is_file():
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verilog_files.append(verilog_main_file)
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use_file = out_verilog / module_name.with_suffix(".use")
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if use_file.is_file():
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with open(out_verilog / module_name.with_suffix(".use")) as f:
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verilog_files.extend(find_verilog_modules(c, f.read().splitlines()))
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if verilog_files:
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print("\nVerilog files for synthesis:")
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for v in verilog_files:
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print(" "+str(v))
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return verilog_files
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@task
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def synth(c, target):
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target = resolve_synth_target(target)
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out_info, out_verilog, out_bsc, out_yosys, out_nextpnr = ensure_build_dirs(target, "info", "verilog", "bsc", "yosys", "nextpnr")
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module_name = Path(f"mk{target.stem}")
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verilog_files = build(c, target)
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if not verilog_files:
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print("\nWARNING: bluespec compile didn't output any verilog files, did you (* synthesize *) something?")
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return
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phase("Logic synthesis")
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yosys_script = out_yosys / "script.ys"
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yosys_json = out_yosys / module_name.with_suffix(".json")
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yosys_report = out_yosys / module_name.with_suffix(".stats")
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yosys_log = out_yosys / module_name.with_suffix(".log")
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yosys_preprocessed = out_yosys / module_name.with_suffix(".v")
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yosys_preprocessed_rtl = out_yosys / module_name.with_suffix(".rtlil")
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yosys_preprocessed_graph = out_yosys / module_name.stem
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yosys_compiled = out_yosys / f"{module_name.stem}_compiled.v"
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with open(yosys_script, "w", encoding="UTF-8") as f:
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f.write(dedent(f"""\
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read_verilog -sv -defer {' '.join(str(f) for f in verilog_files)}
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hierarchy -top {module_name}
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design -push-copy
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synth_lattice -family ecp5 -abc9 -run :map_ram
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opt -full
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clean -purge
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write_verilog -sv {yosys_preprocessed}
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write_rtlil {yosys_preprocessed_rtl}
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show -format dot -colors 1 -stretch -viewer none -prefix {yosys_preprocessed_graph}
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design -pop
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synth_lattice -family ecp5 -abc9 -no-rw-check
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clean -purge
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write_json {yosys_json}
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write_verilog -sv {yosys_compiled}
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tee -o {yosys_report} stat
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"""))
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c.run(f"yosys -q -L {yosys_log} -T {yosys_script}")
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with open(yosys_report) as f:
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ls = f.readlines()[3:]
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print("".join(ls))
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print(f" JSON : {yosys_json}")
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print(f" Log : {yosys_log}")
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print(f" Flat : {yosys_preprocessed}")
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print(f"Compiled : {yosys_compiled}")
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print(f" Dot : {yosys_preprocessed_graph}.dot")
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pin_map = target.parent / "pin_map.lpf"
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if not pin_map.is_file():
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print(f"WARNING: no pin map at {pin_map}, skipping place&route and bitstream generation")
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return
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phase("Place and route")
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nextpnr_out = out_nextpnr / module_name.with_suffix(".pnr")
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nextpnr_log = out_nextpnr / module_name.with_suffix(".log")
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nextpnr_timing = out_nextpnr / module_name.with_suffix(".log")
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out = c.run(f"nextpnr-ecp5 --85k --detailed-timing-report -l {nextpnr_log} --report {nextpnr_timing} --json {yosys_json} --lpf {pin_map} --package=CABGA381 --speed=6 --textcfg {nextpnr_out}", hide='stderr')
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print_filtered_paragraphs(out.stderr, "Device utilisation", "Critical path", "Max frequency", "Max delay", common_prefix="Info: ")
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print(f" PNR : {nextpnr_out}")
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print(f" Log : {nextpnr_log}")
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print(f"Timing : {nextpnr_timing}")
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phase("Bitstream generation")
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bitstream = nextpnr_out.with_suffix(".bit")
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c.run(f"ecppack {nextpnr_out} {bitstream}")
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print(f"Wrote bitstream to {bitstream}")
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@task
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def test(c, target):
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for target in expand_test_target(target):
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out_info, out_sim, out_bsc = ensure_build_dirs(target, "info", "sim", "bsc")
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c.run(f"bsc -show-schedule -aggressive-conditions -check-assert -u -sim -info-dir {out_info} -simdir {out_sim} -bdir {out_bsc} -g mkTB -p {target.parent}:lib:sim:%/Libraries {target}")
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exec = out_sim / "TB"
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c.run(f"bsc -p {out_bsc} -sim -simdir {out_sim} -e mkTB -o {exec}")
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testdata = out_sim / "testdata"
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testdata_tgt = target.parent / "testdata"
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testdata_tgt = testdata_tgt.relative_to(out_sim, walk_up=True)
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testdata.unlink(missing_ok=True)
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testdata.symlink_to(testdata_tgt, target_is_directory=True)
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with c.cd(out_sim):
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c.run(f"./TB -V {target.stem}.vcd")
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@task
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def clean(c):
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if Path("out").is_dir():
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shutil.rmtree("out")
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