322 lines
9.9 KiB
Plaintext
322 lines
9.9 KiB
Plaintext
package MemoryArbiter_Test;
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import Assert::*;
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import StmtFSM::*;
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import Testing::*;
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import Printf::*;
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import List::*;
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import Vector::*;
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import BuildVector::*;
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import MemoryArbiter::*;
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typedef UInt#(4) Addr;
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typedef struct {
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Bool write;
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Addr addr;
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} WriteReq deriving (Bits, Eq);
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typedef struct {
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String name;
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Maybe#(WriteReq) cpu;
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Maybe#(WriteReq) debugger;
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Maybe#(Addr) palette;
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Maybe#(Addr) tile1;
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Maybe#(Addr) tile2;
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Maybe#(Addr) sprite;
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Vector#(6, Bool) want;
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} TestCase deriving (Bits, Eq);
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function Maybe#(WriteReq) rwRead(Addr addr);
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return tagged Valid WriteReq{write: False, addr: addr};
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endfunction
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function Maybe#(WriteReq) rwWrite(Addr addr);
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return tagged Valid WriteReq{write: True, addr: addr};
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endfunction
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function Maybe#(Addr) read(Addr addr);
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return tagged Valid addr;
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endfunction
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function Maybe#(t) idle();
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return tagged Invalid;
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endfunction
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function Vector#(6, Bool) grant(Integer granted_a, Integer granted_b);
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let ret = replicate(False);
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if (granted_a >= 0)
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ret[granted_a] = True;
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if (granted_b >= 0)
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ret[granted_b+3] = True;
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return ret;
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endfunction
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function TestCase testCase(String name,
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Maybe#(WriteReq) cpu,
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Maybe#(WriteReq) debugger,
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Maybe#(Addr) palette,
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Maybe#(Addr) tile1,
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Maybe#(Addr) tile2,
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Maybe#(Addr) sprite,
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Integer portA,
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Integer portB);
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return TestCase{
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name: name,
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cpu: cpu,
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debugger: debugger,
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palette: palette,
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tile1: tile1,
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tile2: tile2,
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sprite: sprite,
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want: grant(portA, portB)
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};
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endfunction
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module mkTB();
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MemoryArbiter#(Addr) dut <- mkMemoryArbiter();
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Vector#(29, TestCase) tests = vec(
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testCase("All idle",
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idle, idle, idle,
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idle, idle, idle,
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-1, -1),
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// Single client accesses at a time
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testCase("CPU read", rwRead(1), idle, idle,
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idle, idle, idle,
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0, -1),
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testCase("CPU write", rwWrite(1), idle, idle,
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idle, idle, idle,
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0, -1),
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testCase("Debugger read",
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idle, rwRead(1), idle,
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idle, idle, idle,
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1, -1),
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testCase("Debugger write",
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idle, rwWrite(1), idle,
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idle, idle, idle,
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1, -1),
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testCase("Palette read",
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idle, idle, read(1),
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idle, idle, idle,
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2, -1),
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testCase("Tile1 read",
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idle, idle, idle,
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read(1), idle, idle,
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-1, 0),
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testCase("Tile2 read",
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idle, idle, idle,
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idle, read(1), idle,
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-1, 1),
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testCase("Sprite read",
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idle, idle, idle,
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idle, idle, read(1),
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-1, 2),
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// Strict priority on port A
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testCase("CPU + Debugger + Palette",
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rwRead(1), rwRead(2), read(3),
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idle, idle, idle,
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0, -1),
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testCase("CPU + Palette",
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rwRead(1), idle, read(3),
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idle, idle, idle,
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0, -1),
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testCase("Debugger + Palette",
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idle, rwRead(2), read(3),
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idle, idle, idle,
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1, -1),
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// Round-robin on port B
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testCase("Sprite read", // to reset round robin
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idle, idle, idle,
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idle, idle, read(1),
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-1, 2),
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testCase("Tile1 + Tile2 + Sprite",
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idle, idle, idle,
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read(1), read(2), read(3),
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-1, 0),
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testCase("Tile1 + Tile2 + Sprite",
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idle, idle, idle,
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read(1), read(2), read(3),
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-1, 1),
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testCase("Tile1 + Tile2 + Sprite",
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idle, idle, idle,
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read(1), read(2), read(3),
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-1, 2),
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testCase("Tile1 + Tile2 + Sprite",
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idle, idle, idle,
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read(1), read(2), read(3),
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-1, 0),
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testCase("Tile1 + Sprite",
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idle, idle, idle,
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read(1), idle, read(3),
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-1, 2),
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testCase("Tile2 + Sprite",
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idle, idle, idle,
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idle, read(2), read(3),
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-1, 1),
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testCase("Tile2 + Sprite",
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idle, idle, idle,
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idle, read(2), read(3),
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-1, 2),
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// Inter-port conflicts
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testCase("Read/read, no conflict",
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rwRead(0), idle, idle,
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read(0), idle, idle,
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0, 0),
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testCase("Write/read, no conflict",
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rwWrite(1), idle, idle,
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read(0), idle, idle,
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0, 0),
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testCase("Tile1 write conflict",
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rwWrite(0), idle, idle,
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read(0), idle, idle,
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0, -1),
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testCase("Tile2 write conflict",
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rwWrite(0), idle, idle,
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idle, read(0), idle,
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0, -1),
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testCase("Sprite write conflict",
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rwWrite(0), idle, idle,
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idle, idle, read(0),
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0, -1),
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testCase("Tile1 write conflict with debugger",
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idle, rwWrite(0), idle,
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read(0), idle, idle,
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1, -1),
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testCase("Sprite read", // to reset round robin
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idle, idle, idle,
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idle, idle, read(1),
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-1, 2),
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testCase("CPU write conflict, other port feasible",
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rwWrite(0), idle, idle,
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read(0), read(1), idle,
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0, 1),
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testCase("CPU write conflict, conflict resolved",
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idle, idle, idle,
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read(0), idle, idle,
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-1, 0));
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Reg#(UInt#(32)) idx <- mkReg(0);
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rule display_test (idx == 0);
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$display("RUN TestMemoryArbiter");
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endrule
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(* no_implicit_conditions, fire_when_enabled *)
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rule input_cpu (tests[idx].cpu matches tagged Valid .req &&& req matches WriteReq {write: .write, addr: .addr});
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dut.cpu.request(write, addr);
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endrule
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(* no_implicit_conditions, fire_when_enabled *)
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rule input_debugger (tests[idx].debugger matches tagged Valid .req &&& req matches WriteReq {write: .write, addr: .addr});
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dut.debugger.request(write, addr);
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endrule
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(* no_implicit_conditions, fire_when_enabled *)
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rule input_palette (tests[idx].palette matches tagged Valid .addr);
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dut.palette.request(addr);
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endrule
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(* no_implicit_conditions, fire_when_enabled *)
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rule input_tile1 (tests[idx].tile1 matches tagged Valid .addr);
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dut.tile1.request(addr);
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endrule
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(* no_implicit_conditions, fire_when_enabled *)
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rule input_tile2 (tests[idx].tile2 matches tagged Valid .addr);
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dut.tile2.request(addr);
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endrule
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(* no_implicit_conditions, fire_when_enabled *)
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rule input_sprite (tests[idx].sprite matches tagged Valid .addr);
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dut.sprite.request(addr);
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endrule
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function Fmt rw_str(Maybe#(WriteReq) v);
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case (v) matches
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tagged Valid .req: begin
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if (req.write)
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return $format("Write(%0d)", req.addr);
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else
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return $format("Read(%0d)", req.addr);
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end
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tagged Invalid: return $format("Idle");
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endcase
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endfunction
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function Fmt ro_str(Maybe#(Addr) v);
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case (v) matches
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tagged Valid .addr: return $format("Read(%0d)", addr);
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tagged Invalid: return $format("Idle");
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endcase
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endfunction
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(* no_implicit_conditions, fire_when_enabled *)
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rule check_grants;
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Vector#(6, Bool) gotVec = newVector;
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gotVec[0] = dut.cpu.grant();
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gotVec[1] = dut.debugger.grant();
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gotVec[2] = dut.palette.grant();
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gotVec[3] = dut.tile1.grant();
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gotVec[4] = dut.tile2.grant();
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gotVec[5] = dut.sprite.grant();
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let test = tests[idx];
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let got = pack(reverse(gotVec));
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let want = pack(reverse(test.want));
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$display("\n # %0d: %s", idx+1, tests[idx].name);
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$display(" input:",
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"\n 0:", rw_str(test.cpu), "\n 1:", rw_str(test.debugger), "\n 2:", ro_str(test.palette),
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"\n 3:", ro_str(test.tile1), "\n 4:", ro_str(test.tile2), "\n 5:", ro_str(test.sprite));
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$display(" got : %03b %03b", got[5:3], got[2:0]);
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$display(" want: %03b %03b", want[5:3], want[2:0]);
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dynamicAssert(got == want, "wrong arbiter output");
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endrule
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(* no_implicit_conditions, fire_when_enabled *)
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rule advance_test;
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let next = idx+1;
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let max = fromInteger(arrayLength(vectorToArray(tests)));
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if (next == max) begin
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$display("OK TestMemoryArbiter");
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$finish;
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end
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else
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idx <= next;
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endrule
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// function Stmt testMemoryArbiter();
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// return seq
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// testCase(idle, idle, idle, idle, idle, idle,
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// grant(-1, -1));
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//
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// // Simple single-client accesses
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// testCase(readA(1), idle, idle, idle, idle, idle,
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// grant(0, -1));
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// testCase(writeA(1), idle, idle, idle, idle, idle,
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// grant(0, -1));
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// testCase(idle, readA(1), idle, idle, idle, idle,
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// grant(1, -1));
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// testCase(idle, writeA(1), idle, idle, idle, idle,
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// grant(1, -1));
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// testCase(idle, idle, read(1), idle, idle, idle,
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// grant(2, -1));
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// testCase(idle, idle, idle, read(1), idle, idle,
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// grant(-1, 0));
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// testCase(idle, idle, idle, idle, read(1), idle,
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// grant(-1, 1));
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// testCase(idle, idle, idle, idle, idle, read(1),
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// grant(-1, 2));
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// endseq;
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// endfunction
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endmodule
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endpackage
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