137 lines
4.4 KiB
Plaintext
137 lines
4.4 KiB
Plaintext
package VRAM_Test;
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import Assert::*;
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import StmtFSM::*;
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import GetPut::*;
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import ClientServer::*;
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import Connectable::*;
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import Vector::*;
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import MemArbiter::*;
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import Testing::*;
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import VRAM::*;
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interface FakeVRAM;
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interface VRAMServer server;
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method Action next_response(VRAMResponse resp);
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method Maybe#(VRAMRequest) last_request();
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endinterface
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module mkFakeVRAM(FakeVRAM);
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Reg#(Maybe#(VRAMRequest)) req <- mkReg(tagged Invalid);
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Reg#(Maybe#(VRAMResponse)) resp <- mkReg(tagged Invalid);
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interface VRAMServer server;
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interface Put request;
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method Action put(r);
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req <= tagged Valid r;
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endmethod
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endinterface
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interface Get response;
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method ActionValue#(VRAMResponse) get() if (resp matches tagged Valid .respval &&& req matches tagged Valid .reqval &&& reqval.data matches tagged Invalid);
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resp <= tagged Invalid;
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return respval;
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endmethod
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endinterface
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endinterface
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method Action next_response(r) if (resp matches tagged Invalid);
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resp <= tagged Valid r;
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endmethod
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method Maybe#(VRAMRequest) last_request();
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return req;
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endmethod
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endmodule
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module mkArbitratedVRAMServersTest(FSM);
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let testflags <- mkTestFlags();
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let cycles <- mkCycleCounter();
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let vram <- mkFakeVRAM();
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MemArbiter#(3, VRAMAddr) arb <- mkPriorityMemArbiter();
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Vector#(3, VRAMServer) ports <- mkArbitratedVRAMServers(vram.server, arb);
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function Action check_read(VRAMServer port, VRAMAddr want_addr, VRAMData want_data);
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return action
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let want_request = VRAMRequest{addr: want_addr, data: tagged Invalid};
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if (testflags.verbose)
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$display("Last received VRAM request: ", fshow(vram.last_request), " want ", fshow(want_request));
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dynamicAssert(vram.last_request == tagged Valid want_request, "wrong request seen by vram for read");
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let got <- port.response.get();
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if (testflags.verbose)
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$display("VRAM.read() = %0d, want %0d", got.data, want_data);
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dynamicAssert(got.data == want_data, "wrong data seen in vram read");
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endaction;
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endfunction
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function Action check_write(VRAMAddr want_addr, VRAMData data);
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return action
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let want = VRAMRequest{addr: want_addr, data: tagged Valid data};
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if (testflags.verbose)
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$display("Last received VRAM request: ", fshow(vram.last_request), " want ", fshow(want));
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dynamicAssert(vram.last_request == tagged Valid want, "wrong request seen by vram for write");
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endaction;
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endfunction
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let fsm <- mkFSM(seq
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// Single write
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ports[1].request.put(VRAMRequest{addr: 123, data: tagged Valid 42});
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check_write(123, 42);
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// Single read
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vram.next_response(VRAMResponse{data: 23});
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ports[1].request.put(VRAMRequest{addr: 124, data: tagged Invalid});
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check_read(ports[1], 124, 23);
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// Concurrent ops, process port 1 response first to check
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// buffering allows port 0 op to finish and port 1 to proceed
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vram.next_response(VRAMResponse{data: 11});
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par
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vram.next_response(VRAMResponse{data: 66});
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ports[0].request.put(VRAMRequest{addr: 123, data: tagged Invalid});
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ports[1].request.put(VRAMRequest{addr: 125, data: tagged Invalid});
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endpar
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check_read(ports[1], 125, 66);
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check_read(ports[0], 125, 11); // note, 125 because the last op is still port 1's read
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endseq);
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return fsm;
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endmodule
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module mkTestFull(FSM);
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let testflags <- mkTestFlags();
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let dut <- mkVRAM(4);
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let fsm <- mkFSM(seq
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dut.cpu.request.put(VRAMRequest{addr: 1, data: tagged Valid 42});
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dut.cpu.request.put(VRAMRequest{addr: 1, data: tagged Invalid});
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action
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let resp <- dut.cpu.response.get();
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if (testflags.verbose)
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$display("vram read: ", fshow(resp));
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dynamicAssert(resp.data == 42, "wrong data read after writing");
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endaction
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endseq);
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return fsm;
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endmodule
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module mkTB();
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let testGlue <- mkArbitratedVRAMServersTest();
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let testFull <- mkTestFull();
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runTest(100,
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mkTest("VRAM", seq
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mkTest("VRAM/Glue", seq
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testGlue.start();
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await(testGlue.done);
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endseq);
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mkTest("VRAM/Full", seq
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testFull.start();
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await(testFull.done);
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endseq);
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endseq));
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endmodule
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endpackage
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