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Graphics Adapter for Retropixel Yeeting. An experiment for now, who knows what might happen.
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David Anderson b46d70fa07 vram/VRAMCore: cycle using prime numbers in tests 
VRAMs are powers of two, so if memory wiring is wrong and we end up
with ram blocks mirrored at several points in the address space, we
want a write pattern that doesn't repeat cleanly on power of two
blocks. That way, a mirrored memory block cannot contain values that
are valid for all its locations.
 		2024-09-09 11:27:53 -07:00
experiments vram/MemArbiter: fix bug with write conflict avoidance 2024-09-08 15:02:55 -07:00
hardware/sentinel65x hardware/sentinel65x: comment out logic 2024-09-08 15:16:34 -07:00
images Add tentative requirements document to capture requests. 2024-08-14 09:39:42 -07:00
lib lib/DelayLine: plumb verbose test flag into tests 2024-09-09 11:20:13 -07:00
scripts Grab the inout port fixer from bsc tree, wire it in 2024-09-06 21:26:39 -07:00
sim Add some early testing harness for the sim DP16KD 2024-08-30 22:14:10 -07:00
vram vram/VRAMCore: cycle using prime numbers in tests 2024-09-09 11:27:53 -07:00
.gitignore add a simple build/test script 2024-08-14 09:39:42 -07:00
.svlint.toml Add svlint config 2024-08-23 00:21:15 -07:00
LICENSE Initial basic files 2024-08-13 22:24:20 -07:00
Requirements.md Requirements.md: fix image insertion syntax 2024-08-14 09:44:14 -07:00
flake.lock flake.lock: update tools 2024-09-06 21:17:32 -07:00
flake.nix sim: implementation of a simulation model DP16KD 2024-08-30 18:54:54 -07:00
tasks.py tasks.py: plumb -v to enable verbose test output 2024-09-09 11:17:08 -07:00