17 lines
668 B
Plaintext
17 lines
668 B
Plaintext
BLOCK RESETPATHS;
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BLOCK ASYNCPATHS;
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SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE;
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LOCATE COMP "CLK" SITE "G2";
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IOBUF PORT "CLK" PULLMODE=NONE IO_TYPE=LVCMOS33;
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FREQUENCY PORT "CLK" 25 MHZ;
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LOCATE COMP "RST_N" SITE "D6"; # BTN_PWRn (inverted logic)
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IOBUF PORT "RST_N" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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LOCATE COMP "debug_serial_out" SITE "L4"; # FPGA transmits to ftdi
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LOCATE COMP "debug_serial_in" SITE "M1"; # FPGA receives from ftdi
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IOBUF PORT "debug_serial_out" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "debug_serial_in" PULLMODE=UP IO_TYPE=LVCMOS33;
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