48 lines
1.2 KiB
Plaintext
48 lines
1.2 KiB
Plaintext
package Top;
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import Connectable::*;
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import GetPut::*;
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import ClientServer::*;
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import PackUnpack::*;
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import UART::*;
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import VRAM::*;
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module mkUARTDebugger(Integer clock_frequency, Integer uart_bitrate, VRAMServer mem, UART_PHY ifc);
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UART _uart <- mkUART(clock_frequency, uart_bitrate);
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disableFlowControl(_uart); // Can't do hardware flow control on ULX3S
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Server#(Bit#(8), VRAMRequest) _decode <- mkUnpacker();
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Server#(VRAMResponse, Bit#(8)) _encode <- mkPacker();
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mkConnection(_uart.receive, _decode.request);
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mkConnection(_decode.response, mem.request);
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mkConnection(mem.response, _encode.request);
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mkConnection(_encode.response, _uart.send);
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return _uart.phy;
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endmodule
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interface Top;
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(* always_enabled,prefix="debug" *)
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method Action debugger_rx_in((* port="serial_in" *) bit b);
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(* always_ready,result="debug_serial_out" *)
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method bit debugger_tx_out();
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endinterface
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(* synthesize *)
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module mkTop(Top);
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////////////
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// Memory
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VRAM mem <- mkVRAM(128);
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////////////
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// Debug interface
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let debugger <- mkUARTDebugger(25_000_000, 115_200, mem.debugger);
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method debugger_rx_in = debugger.rx_in;
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method debugger_tx_out = debugger.tx_out;
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endmodule
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endpackage
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