20 lines
756 B
Plaintext
20 lines
756 B
Plaintext
BLOCK RESETPATHS;
|
|
BLOCK ASYNCPATHS;
|
|
|
|
SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE;
|
|
|
|
LOCATE COMP "CLK" SITE "G2";
|
|
IOBUF PORT "CLK" PULLMODE=NONE IO_TYPE=LVCMOS33;
|
|
FREQUENCY PORT "CLK" 25 MHZ;
|
|
|
|
LOCATE COMP "RST_N" SITE "D6"; # BTN_PWRn (inverted logic)
|
|
IOBUF PORT "RST_N" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
|
|
LOCATE COMP "debug_serial_out" SITE "L4"; # FPGA transmits to ftdi
|
|
LOCATE COMP "debug_serial_in" SITE "M1"; # FPGA receives from ftdi
|
|
IOBUF PORT "debug_serial_out" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
IOBUF PORT "debug_serial_in" PULLMODE=UP IO_TYPE=LVCMOS33;
|
|
|
|
LOCATE COMP "led" SITE "B2";
|
|
IOBUF PORT "led" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|