79 lines
2.0 KiB
Plaintext
79 lines
2.0 KiB
Plaintext
package Top;
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import MemArbiter::*;
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import Vector::*;
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import DReg::*;
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import DelayLine::*;
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import Connectable::*;
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typedef UInt#(2) Addr;
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(* always_ready *)
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interface Top;
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method Action cpu(Bool write, Addr addr);
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method Action debugger(Bool write, Addr addr);
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method Action palette(Addr addr);
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method Action tile1(Addr addr);
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method Action tile2(Addr addr);
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method Action sprite(Addr addr);
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method Bit#(6) grants();
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endinterface
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(* synthesize, clock_prefix="clk_25mhz", reset_prefix="rst_btn" *)
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module mkTop(Top);
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Vector#(6, Reg#(Maybe#(MemArbiterOp#(Addr)))) wrin <- replicateM(mkDReg(tagged Invalid));
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MemArbiter#(3, Addr) portA <- mkPriorityMemArbiter();
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MemArbiter#(3, Addr) portB <- mkRoundRobinMemArbiter();
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mkConnection(portA, portB);
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let arbiters = append(portA.ports, portB.ports);
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Reg#(Vector#(6, Bool)) ok <- mkReg(replicate(False));
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for (Integer i=0; i<6; i=i+1) begin
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rule req (wrin[i] matches tagged Valid .req);
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arbiters[i].request(req);
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endrule
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end
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rule resp;
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function Bool get(MemArbiterServer#(Addr) s);
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return s.grant();
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endfunction
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ok <= map(get, arbiters);
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endrule
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method Action cpu(Bool write, Addr addr);
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wrin[0] <= tagged Valid MemArbiterOp{write: write, addr: addr};
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endmethod
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method Action debugger(Bool write, Addr addr);
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wrin[1] <= tagged Valid MemArbiterOp{write: write, addr: addr};
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endmethod
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method Action palette(Addr addr);
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wrin[2] <= tagged Valid MemArbiterOp{write: False, addr: addr};
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endmethod
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method Action tile1(Addr addr);
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wrin[3] <= tagged Valid MemArbiterOp{write: False, addr: addr};
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endmethod
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method Action tile2(Addr addr);
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wrin[4] <= tagged Valid MemArbiterOp{write: False, addr: addr};
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endmethod
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method Action sprite(Addr addr);
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wrin[5] <= tagged Valid MemArbiterOp{write: False, addr: addr};
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endmethod
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method Bit#(6) grants();
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return pack(ok);
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endmethod
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endmodule
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endpackage
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