David Anderson 6fd040565c Grab the inout port fixer from bsc tree, wire it in ... Yosys doesn't understand Verilog-2001 port aliases. Unfortunately bsc uses those to represent inout ports because it's the only way to represent a particular kind of shared bus in Verilog source code. Thankfully, a kind soul at Bluespec Inc made a perl script that transforms the port alias construct into regular verilog-1995, which works fine in cases like mine where the only user of the inout port is a TriState module which tears it apart into separate input/output/enable signals for the rest of bsc to work with.		2024-09-06 21:26:39 -07:00
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basicinout.pl	Grab the inout port fixer from bsc tree, wire it in	2024-09-06 21:26:39 -07:00