58 lines
1.6 KiB
Plaintext
58 lines
1.6 KiB
Plaintext
package Top;
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// import Connectable::*;
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// import TriState::*;
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// import ClockOut::*;
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// import PLL::*;
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// interface SystemBus;
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// (* always_enabled,prefix="" *)
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// method Action addr(UInt#(24) addr);
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// (* always_enabled,prefix="" *)
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// method Action phi2(bit phi2);
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// (* always_enabled,prefix="" *)
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// method Action write(bit we);
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// endinterface
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// module mkSystemBus(SystemBus);
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// endmodule
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// interface Top;
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// (* always_ready *)
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// method bit clkout();
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// interface SystemBus cpu;
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// endinterface
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// (* synthesize,no_default_clock,no_default_reset,default_gate_unused *)
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// module mkTop(Clock clk_ref,
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// (* clocked_by="no_clock" *) Reset rst,
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// (* clocked_by="no_clock" *) Inout#(Bit#(8)) data,
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// Top ifc);
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// let pll <- mkPLL(clk_ref);
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// let cpu_clk <- mkClockOut(clocked_by(pll.cpu_clk), reset_by(rst));
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// Reg#(Bool) data_out_en <- mkReg(False, clocked_by(pll.cpu_clk), reset_by(rst));
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// Reg#(Bit#(8)) data_out <- mkReg(0, clocked_by(pll.cpu_clk), reset_by(rst));
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// TriState#(Bit#(8)) data_in <- mkTriState(data_out_en, data_out, clocked_by(pll.cpu_clk), reset_by(rst));
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// mkConnection(data, data_in.io);
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// interface SystemBus cpu;
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// method clkout = cpu_clk.value;
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// method Action addr(a);
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// noAction;
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// endmethod
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// method Action phi2(v);
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// noAction;
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// endmethod
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// method Action write(bit we);
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// noAction;
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// endmethod
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// //interface data = data_in.io;
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// endinterface
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// endmodule
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endpackage
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