47 lines
1.7 KiB
Plaintext
47 lines
1.7 KiB
Plaintext
package PinSync;
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// mkPinSync builds a synchronizer for use with asynchronous inputs.
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//
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// You should only use this to capture asynchronous inputs coming from
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// outside your design. For clock domain crossing within your design,
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// use the dual-clocked synchronizers found in Bluespec's standard
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// library.
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//
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// As the name suggests, mkPinSync is intended to be used to
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// synchronize data coming into your design from an external pin, such
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// as the RX line of a UART. Such signals do not run according to a
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// known clock, so the regular stdlib synchronizers cannot be used as
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// there's no "source" clock we can provide them.
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//
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// You can think of mkPinSync as the output end of a standard
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// synchronizer, without the initial register that's clocked by the
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// source domain. Conceptually, we assume that register exists outside
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// our design and is driving the input of mkPinSync, so we just need
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// the metastability mitigation within our own domain.
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(* always_enabled="_write",always_ready="_read" *)
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module mkPinSync(val init_value, Reg#(val) ifc)
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provisos(Bits#(val, _));
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Reg#(val) r1 <- mkReg(init_value);
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Reg#(val) r2 <- mkReg(init_value);
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// To break write+read conflicts. Without this, a rule that
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// atomically reads the sync while also writing it fails to
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// schedule vs. the 'every' rule below. This shouldn't really
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// happen in real designs, but it's a convenient idiom in
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// testing. The wire is free in terms of logic, so might as well
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// make atomic read+write work.
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Wire#(val) out <- mkBypassWire();
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(* no_implicit_conditions, fire_when_enabled *)
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rule every;
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out <= r2;
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r2 <= r1;
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endrule
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method _read = out._read;
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method _write = r1._write;
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endmodule
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endpackage
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