61 lines
1.7 KiB
Verilog
61 lines
1.7 KiB
Verilog
// diamond 3.7 accepts this PLL
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// diamond 3.8-3.9 is untested
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// diamond 3.10 or higher is likely to abort with error about unable to use feedback signal
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// cause of this could be from wrong CPHASE/FPHASE parameters
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module PLL
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(
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input CLK_REF, // 25 MHz, 0 deg
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output CLK_MAIN, // 100 MHz, 0 deg
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output CLK_CPU, // 8 MHz, 0 deg
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output CLK_VGA, // 25 MHz, 0 deg
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output locked
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);
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(* FREQUENCY_PIN_CLKI="25" *)
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(* FREQUENCY_PIN_CLKOP="100" *)
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(* FREQUENCY_PIN_CLKOS="8" *)
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(* FREQUENCY_PIN_CLKOS2="25" *)
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(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
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EHXPLLL #(
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.PLLRST_ENA("DISABLED"),
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.INTFB_WAKE("DISABLED"),
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.STDBY_ENABLE("DISABLED"),
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.DPHASE_SOURCE("DISABLED"),
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.OUTDIVIDER_MUXA("DIVA"),
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.OUTDIVIDER_MUXB("DIVB"),
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.OUTDIVIDER_MUXC("DIVC"),
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.OUTDIVIDER_MUXD("DIVD"),
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.CLKI_DIV(1),
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.CLKOP_ENABLE("ENABLED"),
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.CLKOP_DIV(6),
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.CLKOP_CPHASE(2),
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.CLKOP_FPHASE(0),
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.CLKOS_ENABLE("ENABLED"),
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.CLKOS_DIV(75),
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.CLKOS_CPHASE(2),
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.CLKOS_FPHASE(0),
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.CLKOS2_ENABLE("ENABLED"),
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.CLKOS2_DIV(24),
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.CLKOS2_CPHASE(2),
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.CLKOS2_FPHASE(0),
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.FEEDBK_PATH("CLKOP"),
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.CLKFB_DIV(4)
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) pll_i (
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.RST(1'b0),
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.STDBY(1'b0),
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.CLKI(CLK_REF),
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.CLKOP(CLK_MAIN),
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.CLKOS(CLK_CPU),
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.CLKOS2(CLK_VGA),
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.CLKFB(CLK_MAIN),
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.CLKINTFB(),
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.PHASESEL0(1'b0),
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.PHASESEL1(1'b0),
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.PHASEDIR(1'b1),
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.PHASESTEP(1'b1),
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.PHASELOADREG(1'b1),
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.PLLWAKESYNC(1'b0),
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.ENCLKOP(1'b0),
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.LOCK(locked)
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);
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endmodule
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