100 lines
3.1 KiB
Plaintext
100 lines
3.1 KiB
Plaintext
package VRAM;
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import Connectable::*;
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import GetPut::*;
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import ClientServer::*;
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import Vector::*;
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import FIFOF::*;
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import SpecialFIFOs::*;
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import MemArbiter::*;
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import VRAMCore::*;
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// Re-exports from VRAMCore
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export VRAMAddr, VRAMData, VRAMRequest(..), VRAMResponse(..);
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export VRAMServer(..);
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export VRAM(..), mkVRAM;
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typedef Server#(VRAMRequest, VRAMResponse) VRAMServer;
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// mkArbitratedVRAMServers expands a VRAMServer port into multiple
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// ports through the use of a MemArbiter.
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module mkArbitratedVRAMServers(VRAMServer ram, MemArbiter#(n, VRAMAddr) arb, Vector#(n, VRAMServer) ifc)
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provisos (Min#(n, 1, 1),
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Alias#(port_idx, UInt#(TLog#(n))));
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Vector#(n, FIFOF#(VRAMRequest)) requests <- replicateM(mkBypassFIFOF());
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Vector#(n, FIFOF#(VRAMResponse)) responses <- replicateM(mkBypassFIFOF());
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Reg#(Maybe#(port_idx)) awaiting_response[2] <- mkCReg(2, tagged Invalid);
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(* fire_when_enabled *)
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rule request_ports;
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for (Integer i=0; i<valueOf(n); i=i+1)
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if (requests[i].notEmpty) begin
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let req = requests[i].first;
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let arb_req = MemArbiterOp{
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write: isValid(req.data),
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addr: req.addr
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};
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arb.ports[i].request(arb_req);
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end
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endrule
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(* fire_when_enabled *)
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rule submit (awaiting_response[1] matches tagged Invalid);
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let port = arb.granted_port();
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ram.request.put(requests[port].first);
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requests[port].deq();
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awaiting_response[1] <= tagged Valid port;
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endrule
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(* fire_when_enabled *)
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rule response (awaiting_response[0] matches tagged Valid .port &&& responses[port].notFull);
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let resp <- ram.response.get();
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responses[port].enq(resp);
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awaiting_response[0] <= tagged Invalid;
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endrule
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return map(uncurry(toGPServer), zip(requests, responses));
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endmodule
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// VRAM is a GARY video RAM and its memory ports.
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interface VRAM;
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interface VRAMServer cpu;
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interface VRAMServer debugger;
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interface VRAMServer palette;
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interface VRAMServer tile1;
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interface VRAMServer tile2;
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interface VRAMServer sprite;
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endinterface
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// mkVRAM constructs a VRAM of the requested size. Memory access is
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// spread across two internal ports as follows:
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//
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// Port A: strict most-important-wins priority: CPU, then debugger,
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// then palette DAC.
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// Port B: equal round-robin prioritization between two tile engines
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// and the sprite engine.
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module mkVRAM(Integer num_kilobytes, VRAM ifc);
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VRAMCore ram <- mkVRAMCore(num_kilobytes);
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MemArbiter#(3, VRAMAddr) arbA <- mkPriorityMemArbiter();
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Vector#(3, VRAMServer) portA <- mkArbitratedVRAMServers(ram.portA, arbA);
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MemArbiter#(3, VRAMAddr) arbB <- mkRoundRobinMemArbiter();
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Vector#(3, VRAMServer) portB <- mkArbitratedVRAMServers(ram.portB, arbB);
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// Connect up the arbiters so they correctly prevent write-write
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// and write-read conflicts.
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mkConnection(arbA, arbB);
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interface cpu = portA[0];
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interface debugger = portA[1];
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interface palette = portA[2];
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interface tile1 = portB[0];
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interface tile2 = portB[1];
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interface sprite = portB[2];
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endmodule
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endpackage
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