97 lines
2.3 KiB
Plaintext
97 lines
2.3 KiB
Plaintext
package Top;
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import MemArbiter::*;
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import Vector::*;
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import DReg::*;
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import DelayLine::*;
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typedef UInt#(2) Addr;
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(* always_ready *)
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interface Top;
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method Action cpu(Bool write, Addr addr);
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method Action debugger(Bool write, Addr addr);
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method Action palette(Addr addr);
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method Action tile1(Addr addr);
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method Action tile2(Addr addr);
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method Action sprite(Addr addr);
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method Bit#(6) grants();
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endinterface
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(* synthesize, clock_prefix="clk_25mhz", reset_prefix="rst_btn" *)
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module mkTop(Top);
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Vector#(2, Reg#(Maybe#(MemArbiterWrite#(Addr)))) wrin <- replicateM(mkDReg(tagged Invalid));
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Vector#(4, Reg#(Maybe#(Addr))) rdin <- replicateM(mkDReg(tagged Invalid));
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MemArbiter#(Addr) ret <- mkMemArbiter();
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Reg#(Vector#(6, Bool)) ok <- mkReg(replicate(False));
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rule req_cpu (wrin[0] matches tagged Valid .req);
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ret.cpu.request(req);
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endrule
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rule req_debugger (wrin[1] matches tagged Valid .req);
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ret.debugger.request(req);
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endrule
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rule req_palette (rdin[0] matches tagged Valid .addr);
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ret.palette.request(addr);
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endrule
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rule req_tile1 (rdin[1] matches tagged Valid .addr);
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ret.tile1.request(addr);
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endrule
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rule req_tile2 (rdin[2] matches tagged Valid .addr);
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ret.tile2.request(addr);
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endrule
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rule req_sprite (rdin[3] matches tagged Valid .addr);
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ret.sprite.request(addr);
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endrule
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rule resp;
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Vector#(6, Bool) r = newVector;
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r[0] = ret.cpu.grant();
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r[1] = ret.debugger.grant();
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r[2] = ret.palette.grant();
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r[3] = ret.tile1.grant();
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r[4] = ret.tile2.grant();
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r[5] = ret.sprite.grant();
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ok <= r;
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endrule
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method Action cpu(Bool write, Addr addr);
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wrin[0] <= tagged Valid MemArbiterWrite{write: write, addr: addr};
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endmethod
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method Action debugger(Bool write, Addr addr);
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wrin[1] <= tagged Valid MemArbiterWrite{write: write, addr: addr};
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endmethod
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method Action palette(Addr addr);
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rdin[0] <= tagged Valid addr;
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endmethod
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method Action tile1(Addr addr);
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rdin[1] <= tagged Valid addr;
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endmethod
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method Action tile2(Addr addr);
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rdin[2] <= tagged Valid addr;
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endmethod
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method Action sprite(Addr addr);
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rdin[3] <= tagged Valid addr;
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endmethod
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method Bit#(6) grants();
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return pack(ok);
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endmethod
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endmodule
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endpackage
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