gary/lib/ECP5_RAM.v

183 lines
7.8 KiB
Verilog

module ECP5_RAM(CLKA,
CEA,
OCEA,
WEA,
DIA,
ADA,
CSA,
RSTA,
DOA,
CLKB,
CEB,
OCEB,
WEB,
DIB,
ADB,
CSB,
RSTB,
DOB);
parameter GSR = "ENABLED";
parameter RESETMODE = "SYNC";
parameter ASYNC_RESET_RELEASE = "SYNC";
parameter DATA_WIDTH_A = 18;
parameter REGMODE_A = "NOREG";
parameter WRITEMODE_A = "NORMAL";
parameter CSDECODE_A = "0b000";
parameter DATA_WIDTH_B = 18;
parameter REGMODE_B = "NOREG";
parameter WRITEMODE_B = "NORMAL";
parameter CSDECODE_B = "0b000";
input CLKA;
input CEA;
input OCEA;
input WEA;
input [17:0] DIA;
input [13:0] ADA;
input [2:0] CSA;
input RSTA;
output [17:0] DOA;
input CLKB;
input CEB;
input OCEB;
input WEB;
input [17:0] DIB;
input [13:0] ADB;
input [2:0] CSB;
input RSTB;
output [17:0] DOB;
DP16KD#(.GSR(GSR),
.RESETMODE(RESETMODE),
.ASYNC_RESET_RELEASE(ASYNC_RESET_RELEASE),
.DATA_WIDTH_A(DATA_WIDTH_A),
.REGMODE_A(REGMODE_A),
.WRITEMODE_A(WRITEMODE_A),
.CSDECODE_A(CSDECODE_A),
.DATA_WIDTH_B(DATA_WIDTH_B),
.REGMODE_B(REGMODE_B),
.WRITEMODE_B(WRITEMODE_B),
.CSDECODE_B(CSDECODE_B)) ram(.CLKA(CLKA),
.CEA(CEA),
.OCEA(OCEA),
.WEA(WEA),
.DIA17(DIA[17]),
.DIA16(DIA[16]),
.DIA15(DIA[15]),
.DIA14(DIA[14]),
.DIA13(DIA[13]),
.DIA12(DIA[12]),
.DIA11(DIA[11]),
.DIA10(DIA[10]),
.DIA9(DIA[9]),
.DIA8(DIA[8]),
.DIA7(DIA[7]),
.DIA6(DIA[6]),
.DIA5(DIA[5]),
.DIA4(DIA[4]),
.DIA3(DIA[3]),
.DIA2(DIA[2]),
.DIA1(DIA[1]),
.DIA0(DIA[0]),
.ADA13(ADA[13]),
.ADA12(ADA[12]),
.ADA11(ADA[11]),
.ADA10(ADA[10]),
.ADA9(ADA[9]),
.ADA8(ADA[8]),
.ADA7(ADA[7]),
.ADA6(ADA[6]),
.ADA5(ADA[5]),
.ADA4(ADA[4]),
.ADA3(ADA[3]),
.ADA2(ADA[2]),
.ADA1(ADA[1]),
.ADA0(ADA[0]),
.CSA2(CSA[2]),
.CSA1(CSA[1]),
.CSA0(CSA[0]),
.RSTA(RSTA),
.DOA17(DOA[17]),
.DOA16(DOA[16]),
.DOA15(DOA[15]),
.DOA14(DOA[14]),
.DOA13(DOA[13]),
.DOA12(DOA[12]),
.DOA11(DOA[11]),
.DOA10(DOA[10]),
.DOA9(DOA[9]),
.DOA8(DOA[8]),
.DOA7(DOA[7]),
.DOA6(DOA[6]),
.DOA5(DOA[5]),
.DOA4(DOA[4]),
.DOA3(DOA[3]),
.DOA2(DOA[2]),
.DOA1(DOA[1]),
.DOA0(DOA[0]),
.CLKB(CLKB),
.CEB(CEB),
.OCEB(OCEB),
.WEB(WEB),
.DIB17(DIB[17]),
.DIB16(DIB[16]),
.DIB15(DIB[15]),
.DIB14(DIB[14]),
.DIB13(DIB[13]),
.DIB12(DIB[12]),
.DIB11(DIB[11]),
.DIB10(DIB[10]),
.DIB9(DIB[9]),
.DIB8(DIB[8]),
.DIB7(DIB[7]),
.DIB6(DIB[6]),
.DIB5(DIB[5]),
.DIB4(DIB[4]),
.DIB3(DIB[3]),
.DIB2(DIB[2]),
.DIB1(DIB[1]),
.DIB0(DIB[0]),
.ADB13(ADB[13]),
.ADB12(ADB[12]),
.ADB11(ADB[11]),
.ADB10(ADB[10]),
.ADB9(ADB[9]),
.ADB8(ADB[8]),
.ADB7(ADB[7]),
.ADB6(ADB[6]),
.ADB5(ADB[5]),
.ADB4(ADB[4]),
.ADB3(ADB[3]),
.ADB2(ADB[2]),
.ADB1(ADB[1]),
.ADB0(ADB[0]),
.CSA2(CSA[2]),
.CSA1(CSA[1]),
.CSA0(CSA[0]),
.RSTB(RSTB),
.DOB17(DOB[17]),
.DOB16(DOB[16]),
.DOB15(DOB[15]),
.DOB14(DOB[14]),
.DOB13(DOB[13]),
.DOB12(DOB[12]),
.DOB11(DOB[11]),
.DOB10(DOB[10]),
.DOB9(DOB[9]),
.DOB8(DOB[8]),
.DOB7(DOB[7]),
.DOB6(DOB[6]),
.DOB5(DOB[5]),
.DOB4(DOB[4]),
.DOB3(DOB[3]),
.DOB2(DOB[2]),
.DOB1(DOB[1]),
.DOB0(DOB[0]));
endmodule