package Top;

import ECP5_RAM::*;

//(* always_enabled *)
interface Top;
   interface EBRPort#(Bit#(12), Bit#(4)) ram1;
   //interface EBRPort#(Bit#(14), Bit#(1)) ram2;
   interface EBRPort#(void, void) ram2;
endinterface

(* synthesize *)
module mkTop(Clock clk2, Reset rst2, Top ifc);
   EBRPortConfig cfgA = defaultValue;
   cfgA.write_mode = Normal;
   EBRPortConfig cfgB = defaultValue;
   cfgB.clk = tagged Valid clk2;
   cfgB.rstN = tagged Valid rst2;
   cfgB.register_output = True;
   let r <- mkEBR(cfgA, cfgB);

   interface EBRPort ram1 = r.portA;
   interface EBRPort ram2 = r.portB;
endmodule

endpackage