package DelayLine_Test;

import Assert::*;
import StmtFSM::*;
import Testing::*;
import Printf::*;
import List::*;

import DelayLine::*;

module mkTB();
   let cycles <- mkCycleCounter();

   function Stmt testDelayLine(DelayLine#(Int#(8)) delay, Bit#(32) wantDelay);
      seq
         action
            delay <= 42;
            cycles.reset();
            $display("  write cycle: %0d", cycles.all);
         endaction

         repeat (wantDelay-1)
         action
            if (delay.ready) begin
               $display("delay line ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all);
               $finish;
            end
         endaction

         // Check the value coming off the delay line and the timing
         // separately, since the delay line read can be blocked by
         // implicit conditions.
         par
            dynamicAssert(delay == 42, "delay output was wrong value");

            action
               dynamicAssert(delay.ready == True, "delay line not ready when expected");
               if (cycles != wantDelay) begin
                  $display("delay line became ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all);
                  $finish;
               end
               $display("  read cycle: %0d", cycles.all);
            endaction
         endpar

         dynamicAssert(delay.ready == False, "delay line still ready after value yield");
      endseq;
   endfunction

   let delay0 <- mkDelayLine(0);
   let delay1 <- mkDelayLine(1);
   let delay2 <- mkDelayLine(2);
   let delay3 <- mkDelayLine(3);
   let delay4 <- mkDelayLine(4);

   let test0 = seq
                  dynamicAssert(delay0.ready == False, "delay line ready before put");

                  par
                     action
                        delay0 <= 42;
                        $display("  write cycle: %0d", cycles.all);
                     endaction
                     action
                        dynamicAssert(delay0.ready == True, "delay line not ready on same cycle");
                        $display("  read cycle: %0d", cycles.all);
                     endaction
                     dynamicAssert(delay0 == 42, "delay line has wrong value");
                  endpar

                  dynamicAssert(delay0.ready == False, "delay line ready without write");
               endseq;


   runTest(100,
      mkTest("DelayLine", seq
         mkTest("DelayLine/0", test0);
         mkTest("DelayLine/1", testDelayLine(delay1, 1));
         mkTest("DelayLine/2", testDelayLine(delay2, 2));
         mkTest("DelayLine/3", testDelayLine(delay3, 3));
         mkTest("DelayLine/4", testDelayLine(delay4, 4));
      endseq));
endmodule

endpackage