package Top;

import ECP5_RAM::*;

(* synthesize *)
module mkTop(ECP5_EBRCorePort#(Bit#(12), Bit#(8)));
   let clk <- exposeCurrentClock;
   let rstN <- exposeCurrentReset;

   ECP5_EBRPortConfig cfg = defaultValue;
   ECP5_EBRCore#(Bit#(12), Bit#(8), UInt#(12), UInt#(8)) ram <- mkECP5_EBRCoreByte(cfg, cfg);

   method put = ram.portA.put;
   method read = ram.portA.read;
endmodule

endpackage