package Top;

import VRAM::*;
import ECP5_RAM::*;
import TriState::*;

(* always_enabled *)
interface Top;
   method Action phi2(bit v);
   method Action we(bit we);
   method Action addr(UInt#(24) addr);
   interface InOut#(Bit#(8)) data();
endinterface

(* synthesize *)
module mkTop(Top);
   Reg#(PortReq) reqA <- mkRegU();
   Reg#(VRAMData) respA <- mkRegU();

   let _ret <- mkByteRAMArray(8);

   rule putA;
      _ret.portA.put(reqA.chip_select, reqA.write, reqA.addr, reqA.datain);
   endrule

   rule getA;
      respA <= _ret.portA.read();
   endrule

   method portA_read = respA._read;
   method Action portA_put(cs, w, a, d);
      reqA <= PortReq{chip_select: cs, write: w, addr: a, datain: d};
   endmethod
   method portB_read = _ret.portB.read;
   method portB_put = _ret.portB.put;
endmodule

endpackage