package Top;

import Connectable::*;
import TriState::*;

import ClockOut::*;
import PLL::*;

interface SystemBus;
   (* always_enabled,prefix="" *)
   method Action addr(UInt#(24) addr);
   (* always_enabled,prefix="" *)
   method Action phi2(bit phi2);
   (* always_enabled,prefix="" *)
   method Action write(bit we);
endinterface

module mkSystemBus(SystemBus);

endmodule

interface Top;
   (* always_ready *)
   method bit clkout();

   interface SystemBus cpu;
endinterface

(* synthesize,no_default_clock,no_default_reset,default_gate_unused *)
module mkTop(Clock clk_ref,
             (* clocked_by="no_clock" *) Reset rst,
             (* clocked_by="no_clock" *) Inout#(Bit#(8)) data,
             Top ifc);
   let pll <- mkPLL(clk_ref);
   let cpu_clk <- mkClockOut(clocked_by(pll.cpu_clk), reset_by(rst));

   Reg#(Bool) data_out_en <- mkReg(False, clocked_by(pll.cpu_clk), reset_by(rst));
   Reg#(Bit#(8)) data_out <- mkReg(0, clocked_by(pll.cpu_clk), reset_by(rst));
   TriState#(Bit#(8)) data_in <- mkTriState(data_out_en, data_out, clocked_by(pll.cpu_clk), reset_by(rst));
   mkConnection(data, data_in.io);

   interface SystemBus cpu;
      method clkout = cpu_clk.value;
      method Action addr(a);
         noAction;
      endmethod
      method Action phi2(v);
         noAction;
      endmethod
      method Action write(bit we);
         noAction;
      endmethod
      //interface data = data_in.io;
   endinterface
endmodule

endpackage