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e5aabcbf4a
...
81e5264d22
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@ -4,7 +4,6 @@ import MemArbiter::*;
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import Vector::*;
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import DReg::*;
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import DelayLine::*;
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import Connectable::*;
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typedef UInt#(2) Addr;
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@ -23,51 +22,70 @@ endinterface
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(* synthesize, clock_prefix="clk_25mhz", reset_prefix="rst_btn" *)
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module mkTop(Top);
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Vector#(6, Reg#(Maybe#(MemArbiterOp#(Addr)))) wrin <- replicateM(mkDReg(tagged Invalid));
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Vector#(2, Reg#(Maybe#(MemArbiterWrite#(Addr)))) wrin <- replicateM(mkDReg(tagged Invalid));
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Vector#(4, Reg#(Maybe#(Addr))) rdin <- replicateM(mkDReg(tagged Invalid));
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MemArbiter#(3, Addr) portA <- mkPriorityMemArbiter();
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MemArbiter#(3, Addr) portB <- mkRoundRobinMemArbiter();
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mkConnection(portA, portB);
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let arbiters = append(portA.ports, portB.ports);
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MemArbiter#(Addr) ret <- mkMemArbiter();
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Reg#(Vector#(6, Bool)) ok <- mkReg(replicate(False));
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for (Integer i=0; i<6; i=i+1) begin
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rule req (wrin[i] matches tagged Valid .req);
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arbiters[i].request(req);
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endrule
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end
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rule req_cpu (wrin[0] matches tagged Valid .req);
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ret.cpu.request(req);
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endrule
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rule req_debugger (wrin[1] matches tagged Valid .req);
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ret.debugger.request(req);
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endrule
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rule req_palette (rdin[0] matches tagged Valid .addr);
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ret.palette.request(addr);
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endrule
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rule req_tile1 (rdin[1] matches tagged Valid .addr);
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ret.tile1.request(addr);
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endrule
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rule req_tile2 (rdin[2] matches tagged Valid .addr);
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ret.tile2.request(addr);
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endrule
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rule req_sprite (rdin[3] matches tagged Valid .addr);
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ret.sprite.request(addr);
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endrule
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rule resp;
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function Bool get(MemArbiterServer#(Addr) s);
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return s.grant();
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endfunction
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ok <= map(get, arbiters);
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Vector#(6, Bool) r = newVector;
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r[0] = ret.cpu.grant();
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r[1] = ret.debugger.grant();
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r[2] = ret.palette.grant();
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r[3] = ret.tile1.grant();
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r[4] = ret.tile2.grant();
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r[5] = ret.sprite.grant();
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ok <= r;
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endrule
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method Action cpu(Bool write, Addr addr);
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wrin[0] <= tagged Valid MemArbiterOp{write: write, addr: addr};
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wrin[0] <= tagged Valid MemArbiterWrite{write: write, addr: addr};
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endmethod
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method Action debugger(Bool write, Addr addr);
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wrin[1] <= tagged Valid MemArbiterOp{write: write, addr: addr};
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wrin[1] <= tagged Valid MemArbiterWrite{write: write, addr: addr};
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endmethod
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method Action palette(Addr addr);
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wrin[2] <= tagged Valid MemArbiterOp{write: False, addr: addr};
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rdin[0] <= tagged Valid addr;
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endmethod
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method Action tile1(Addr addr);
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wrin[3] <= tagged Valid MemArbiterOp{write: False, addr: addr};
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rdin[1] <= tagged Valid addr;
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endmethod
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method Action tile2(Addr addr);
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wrin[4] <= tagged Valid MemArbiterOp{write: False, addr: addr};
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rdin[2] <= tagged Valid addr;
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endmethod
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method Action sprite(Addr addr);
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wrin[5] <= tagged Valid MemArbiterOp{write: False, addr: addr};
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rdin[3] <= tagged Valid addr;
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endmethod
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method Bit#(6) grants();
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@ -1,12 +1,12 @@
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package Top;
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import VRAMCore::*;
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import VRAM::*;
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import ECP5_RAM::*;
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import TriState::*;
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(* synthesize *)
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module mkTop(VRAMCore);
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let _ret <- mkVRAMCore(112);
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module mkTop(VRAM);
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let _ret <- mkVRAM(112);
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return _ret;
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endmodule
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@ -3,45 +3,30 @@ package MemArbiter;
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import Connectable::*;
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import Vector::*;
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export MemArbiterOp(..);
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export MemArbiterWrite(..);
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export MemArbiterServer(..);
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export MemArbiterClient(..);
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export MemArbiter(..), mkPriorityMemArbiter, mkRoundRobinMemArbiter;
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export MemArbiter(..);
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export mkMemArbiter;
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// A MemArbiterOp is an operation that a client is seeking permission
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// to perform.
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typedef struct {
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Bool write;
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addr addr;
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} MemArbiterOp#(type addr) deriving (Bits, Eq, FShow);
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function Bool mem_ops_conflict(Maybe#(MemArbiterOp#(addr)) a, Maybe#(MemArbiterOp#(addr)) b)
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provisos(Eq#(addr));
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if (a matches tagged Valid .ar &&& b matches tagged Valid .br &&& ar.addr == br.addr)
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return ar.write || br.write;
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else
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return False;
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endfunction
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// A MemArbiterServer receives requests and emits grants.
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(* always_ready *)
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interface MemArbiterServer#(type addr);
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method Action request(MemArbiterOp#(addr) req);
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// A MemArbiterServer receives requests for memory access and emits
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// grants.
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interface MemArbiterServer#(type request);
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method Action request(request req);
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method Bool grant();
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endinterface
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// A MemArbiterClient emits requests and receives grants.
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interface MemArbiterClient#(type addr);
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method Maybe#(MemArbiterOp#(addr)) request();
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// A MemArbiterClient emits requests for memory access and emits
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// grants.
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interface MemArbiterClient#(type request);
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method request request();
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method Action grant();
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endinterface
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// Arbiter clients and servers can be connected in the obvious way.
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instance Connectable#(MemArbiterClient#(addr), MemArbiterServer#(addr));
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module mkConnection(MemArbiterClient#(addr) client, MemArbiterServer#(addr) server, Empty ifc);
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rule send_request (client.request matches tagged Valid .req);
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server.request(req);
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instance Connectable#(MemArbiterClient#(req), MemArbiterServer#(req));
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module mkConnection(MemArbiterClient#(req) client, MemArbiterServer#(req) server, Empty ifc);
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rule send_request;
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server.request(client.request());
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endrule
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rule send_grant (server.grant());
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@ -50,173 +35,157 @@ instance Connectable#(MemArbiterClient#(addr), MemArbiterServer#(addr));
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endmodule
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endinstance
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// A MemArbiter manages concurrent access to a memory port.
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interface MemArbiter#(numeric type num_clients, type addr);
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// ports allow clients to request memory access.
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interface Vector#(num_clients, MemArbiterServer#(addr)) ports;
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typedef struct {
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Bool write;
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addr addr;
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} MemArbiterWrite#(type addr) deriving (Bits, Eq);
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// The following methods are to support arbiter chaining.
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//
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// Suppose you're arbitrating access to a dual-port
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// memory. Typically, such a memory specifies that if one port is
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// writing to an address, the other must not concurrently read or
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// write that same address. This means the arbiters attached to
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// each memory port must cooperate to avoid simultaneously granting
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// conflicting requests from their clients.
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//
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// Calling conflict prevents the arbiter from granting a concurrent
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// request that would result in a write-write, read-write or
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// write-read conflict. granted_op emits the operation that the
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// arbiter is granting, if any.
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//
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// MemArbiter intances are Connectable: mkConnection(a, b) gives
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// conflict priority to a. That is, b only grants requests that
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// don't conflict with a's grant.
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(* always_ready *)
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method Action conflict(MemArbiterOp#(addr) conflict);
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method MemArbiterOp#(addr) granted_op();
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// A MemArbiter manages concurrent access to memory ports.
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interface MemArbiter#(type addr);
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interface MemArbiterServer#(MemArbiterWrite#(addr)) cpu;
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interface MemArbiterServer#(MemArbiterWrite#(addr)) debugger;
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interface MemArbiterServer#(addr) palette;
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interface MemArbiterServer#(addr) tile1;
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interface MemArbiterServer#(addr) tile2;
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interface MemArbiterServer#(addr) sprite;
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endinterface
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instance Connectable#(MemArbiter#(m, addr), MemArbiter#(n, addr));
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module mkConnection(MemArbiter#(m, addr) a, MemArbiter#(n, addr) b, Empty ifc);
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(* fire_when_enabled *)
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rule forward_conflict;
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b.conflict(a.granted_op);
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endrule
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endmodule
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endinstance
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// mkMemArbiter builds a GARY memory arbiter.
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//
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// Port A arbitrates with strict priority: CPU requests go first, then
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// the debugger, then the palette DAC.
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//
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// Port B does round-robin arbitration, giving each client a fair
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// share of memory access.
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module mkMemArbiter(MemArbiter#(addr))
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provisos(Bits#(addr, _),
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Eq#(addr),
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Alias#(write_req, MemArbiterWrite#(addr)));
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// mkPriorityMemArbiter returns a MemArbiter that gives priority to
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// lower numbered ports.
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module mkPriorityMemArbiter(MemArbiter#(num_clients, addr))
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provisos (Bits#(addr, _),
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Eq#(addr),
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Min#(num_clients, 1, 1));
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//////
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// Port A users
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Vector#(num_clients, RWire#(MemArbiterOp#(addr))) reqs <- replicateM(mkRWire());
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Wire#(Vector#(num_clients, Bool)) grants <- mkBypassWire();
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RWire#(write_req) cpu_req <- mkRWire();
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RWire#(write_req) debugger_req <- mkRWire();
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PulseWire palette_req <- mkPulseWire();
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RWire#(MemArbiterOp#(addr)) conflict_in <- mkRWire();
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RWire#(MemArbiterOp#(addr)) granted_op_out <- mkRWire();
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PulseWire cpu_ok <- mkPulseWire();
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PulseWire debugger_ok <- mkPulseWire();
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PulseWire palette_ok <- mkPulseWire();
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(* no_implicit_conditions, fire_when_enabled *)
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rule grant_requests;
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Vector#(num_clients, Bool) grant = replicate(False);
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Bool done = False;
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// Address written to by port A, if any. Used to block port B
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// clients that are trying to read the same address.
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RWire#(addr) written_addr <- mkRWire();
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for (Integer i=0; i<valueOf(num_clients); i=i+1) begin
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if (reqs[i].wget() matches tagged Valid .req &&&
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!mem_ops_conflict(conflict_in.wget(), reqs[i].wget()) &&&
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!done) begin
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done = True;
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grant[i] = True;
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granted_op_out.wset(req);
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end
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end
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// We could be fancy with rule conditions to express the priorities
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// between clients, but Bluespec has the preempts annotation to
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// express the ranking directly.
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(* preempts = "grant_cpu, (grant_debugger, grant_palette)" *)
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(* preempts = "grant_debugger, grant_palette" *)
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grants <= grant;
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(* fire_when_enabled *)
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rule grant_cpu (cpu_req.wget matches tagged Valid .req);
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cpu_ok.send();
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if (req.write)
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written_addr.wset(req.addr);
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endrule
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Vector#(num_clients, MemArbiterServer#(addr)) _ifcs = newVector();
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for (Integer i=0; i<valueOf(num_clients); i=i+1)
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_ifcs[i] = (interface MemArbiterServer#(addr);
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method request = reqs[i].wset;
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method grant = grants[i];
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endinterface);
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interface ports = _ifcs;
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method conflict = conflict_in.wset;
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method MemArbiterOp#(addr) granted_op() if (granted_op_out.wget() matches tagged Valid .op);
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return op;
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endmethod
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endmodule
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typedef struct {
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Vector#(n, Bool) grant_vec;
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Maybe#(MemArbiterOp#(addr)) granted_op;
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} GrantResult#(numeric type n, type addr) deriving (Bits, Eq, FShow);
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// select_grant computes which one entry of requests should be
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// granted. Priority order is descending starting from
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// requests[hipri].
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function GrantResult#(n, addr) select_grant(Vector#(n, Maybe#(MemArbiterOp#(addr))) requests,
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UInt#(TLog#(n)) hipri,
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Maybe#(MemArbiterOp#(addr)) conflict)
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provisos (Eq#(addr));
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function onehot(idx);
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let ret = replicate(False);
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ret[idx] = True;
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return ret;
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endfunction
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function GrantResult#(n, addr) do_fold(GrantResult#(n, addr) acc,
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Tuple2#(UInt#(TLog#(n)),
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Maybe#(MemArbiterOp#(addr))) next);
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match {.idx, .mreq} = next;
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if (mreq matches tagged Valid .req &&& acc.granted_op matches tagged Invalid &&& !mem_ops_conflict(conflict, mreq))
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return GrantResult{
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grant_vec: onehot(idx),
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granted_op: tagged Valid req
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};
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else
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// Previous grant won, not requesting, or request not satisfiable.
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return acc;
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endfunction
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let in = zip(map(fromInteger, genVector()), requests);
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let rot = rotateBy(in, fromInteger(valueOf(n)-1)-hipri+1);
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let seed = GrantResult{
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grant_vec: replicate(False),
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granted_op: tagged Invalid
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};
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return foldl(do_fold, seed, rot);
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endfunction
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module mkRoundRobinMemArbiter(MemArbiter#(num_clients, addr))
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provisos (Bits#(addr, _),
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Eq#(addr),
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Min#(num_clients, 1, 1));
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Vector#(num_clients, RWire#(MemArbiterOp#(addr))) reqs <- replicateM(mkRWire);
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Wire#(Vector#(num_clients, Bool)) grants <- mkBypassWire();
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RWire#(MemArbiterOp#(addr)) conflict_in <- mkRWire();
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RWire#(MemArbiterOp#(addr)) granted_op_out <- mkRWire();
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// high_prio is the index of the client that should be first in
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// line to receive access. Every time we grant access to a client,
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// the one after that in sequence becomes high_prio in the next
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// round.
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Reg#(UInt#(TLog#(num_clients))) high_prio <- mkReg(0);
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function Maybe#(_t) get_mreq(RWire#(_t) w);
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return w.wget();
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endfunction
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rule grant;
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let in = map(get_mreq, reqs);
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let res = select_grant(in, high_prio, conflict_in.wget());
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grants <= res.grant_vec;
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if (res.granted_op matches tagged Valid .op) begin
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granted_op_out.wset(op);
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high_prio <= validValue(findElem(True, rotateR(res.grant_vec)));
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end
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rule grant_debugger (debugger_req.wget matches tagged Valid .req);
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debugger_ok.send();
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if (req.write)
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written_addr.wset(req.addr);
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endrule
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Vector#(num_clients, MemArbiterServer#(addr)) _ifcs = newVector();
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for (Integer i=0; i<valueOf(num_clients); i=i+1)
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_ifcs[i] = (interface MemArbiterServer#(addr);
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method request = reqs[i].wset;
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method grant = grants[i];
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endinterface);
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rule grant_palette (palette_req);
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palette_ok.send();
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endrule
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interface ports = _ifcs;
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method conflict = conflict_in.wset;
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method MemArbiterOp#(addr) granted_op() if (granted_op_out.wget() matches tagged Valid .op);
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return op;
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endmethod
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//////
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// Port B users
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Vector#(3, RWire#(addr)) portB_req <- replicateM(mkRWire);
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Wire#(Vector#(3, Bool)) portB_grant <- mkBypassWire();
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Vector#(3, Bool) init = replicate(False); init[0] = True;
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Reg#(Vector#(3, Bool)) priority_vec <- mkReg(init);
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rule grant_portB;
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Vector#(3, Bool) grants = replicate(False);
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Bool port_available = False;
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// This algorithm is a little mystifying at first glance, but it
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// works. priority_vec has one bool per client, only one of
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// which is True. That True bit identifies the client with the
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// highest priority on the next request.
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//
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// This loop goes through each client twice, using
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// port_available to track whether a client can grab the port or
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// not. When we start iterating, the port is marked unavailable
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// until we reach the top priority client, at which point we
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// mark the port available and keep scanning. That effectively
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// makes the search for a requesting client start at the top
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// priority one.
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//
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// As we loop back around a second time, the availability bool
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// gets reset again, but if you take the example of the True bit
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// being in the middle of the vector, and consider cases where
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// the first requestor is before/after that starting point,
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// you'll see that it all works out, and at the end of the loop
|
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// we have a new bit vector where only one client is True - the
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// one whose request is granted.
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for (Integer i = 0; i < 6; i=i+1) begin
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Integer idx = i % 3;
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if (priority_vec[idx])
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port_available = True;
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let req = portB_req[idx].wget();
|
||||
if (port_available && isValid(req) && req != written_addr.wget()) begin
|
||||
port_available = False;
|
||||
grants[idx] = True;
|
||||
end
|
||||
end
|
||||
portB_grant <= grants;
|
||||
// If we granted a request, the grantee becomes the lowest
|
||||
// priority client for the next round of requests. If nobody
|
||||
// requested anything, keep the same priority as before.
|
||||
if (any(id, grants))
|
||||
priority_vec <= rotateR(grants);
|
||||
endrule
|
||||
|
||||
//////
|
||||
// External interface
|
||||
|
||||
interface MemArbiterServer cpu;
|
||||
method request = cpu_req.wset;
|
||||
method grant = cpu_ok;
|
||||
endinterface
|
||||
|
||||
interface MemArbiterServer debugger;
|
||||
method request = debugger_req.wset;
|
||||
method grant = debugger_ok;
|
||||
endinterface
|
||||
|
||||
interface MemArbiterServer palette;
|
||||
method Action request(addr);
|
||||
palette_req.send();
|
||||
endmethod
|
||||
method grant = palette_ok;
|
||||
endinterface
|
||||
|
||||
interface MemArbiterServer tile1;
|
||||
method request = portB_req[0].wset;
|
||||
method grant = portB_grant[0];
|
||||
endinterface
|
||||
|
||||
interface MemArbiterServer tile2;
|
||||
method request = portB_req[1].wset;
|
||||
method grant = portB_grant[1];
|
||||
endinterface
|
||||
|
||||
interface MemArbiterServer sprite;
|
||||
method request = portB_req[2].wset;
|
||||
method grant = portB_grant[2];
|
||||
endinterface
|
||||
endmodule
|
||||
|
||||
endpackage
|
||||
|
|
|
|||
|
|
@ -14,307 +14,282 @@ typedef UInt#(4) Addr;
|
|||
|
||||
typedef struct {
|
||||
String name;
|
||||
Maybe#(MemArbiterWrite#(Addr)) cpu;
|
||||
Maybe#(MemArbiterWrite#(Addr)) debugger;
|
||||
Maybe#(Addr) palette;
|
||||
Maybe#(Addr) tile1;
|
||||
Maybe#(Addr) tile2;
|
||||
Maybe#(Addr) sprite;
|
||||
|
||||
Vector#(n, Maybe#(MemArbiterOp#(Addr))) reqs;
|
||||
Maybe#(MemArbiterOp#(Addr)) conflict;
|
||||
Vector#(6, Bool) want;
|
||||
} TestCase deriving (Bits, Eq);
|
||||
|
||||
Vector#(n, Bool) want_grants;
|
||||
Maybe#(MemArbiterOp#(Addr)) want_granted_op;
|
||||
} TestCase#(numeric type n) deriving (Bits, Eq);
|
||||
|
||||
function Maybe#(MemArbiterOp#(Addr)) read(Addr addr);
|
||||
return tagged Valid MemArbiterOp{write: False, addr: addr};
|
||||
function Maybe#(MemArbiterWrite#(Addr)) rwRead(Addr addr);
|
||||
return tagged Valid MemArbiterWrite{write: False, addr: addr};
|
||||
endfunction
|
||||
|
||||
function Maybe#(MemArbiterOp#(Addr)) write(Addr addr);
|
||||
return tagged Valid MemArbiterOp{write: True, addr: addr};
|
||||
function Maybe#(MemArbiterWrite#(Addr)) rwWrite(Addr addr);
|
||||
return tagged Valid MemArbiterWrite{write: True, addr: addr};
|
||||
endfunction
|
||||
|
||||
function Maybe#(MemArbiterOp#(Addr)) idle();
|
||||
function Maybe#(Addr) read(Addr addr);
|
||||
return tagged Valid addr;
|
||||
endfunction
|
||||
|
||||
function Maybe#(t) idle();
|
||||
return tagged Invalid;
|
||||
endfunction
|
||||
|
||||
function Maybe#(MemArbiterOp#(Addr)) noConflict();
|
||||
return tagged Invalid;
|
||||
function Vector#(6, Bool) grant(Integer granted_a, Integer granted_b);
|
||||
let ret = replicate(False);
|
||||
if (granted_a >= 0)
|
||||
ret[granted_a] = True;
|
||||
if (granted_b >= 0)
|
||||
ret[granted_b+3] = True;
|
||||
return ret;
|
||||
endfunction
|
||||
|
||||
function Vector#(n, Bool) grant(Integer granted);
|
||||
function gen(idx);
|
||||
return idx == granted;
|
||||
endfunction
|
||||
|
||||
return genWith(gen);
|
||||
endfunction
|
||||
|
||||
function Vector#(n, Bool) noGrant();
|
||||
return replicate(False);
|
||||
endfunction
|
||||
|
||||
function TestCase#(n) testCase(String name,
|
||||
Vector#(n, Maybe#(MemArbiterOp#(Addr))) reqs,
|
||||
Maybe#(MemArbiterOp#(Addr)) conflict,
|
||||
Vector#(n, Bool) want_grants,
|
||||
Maybe#(MemArbiterOp#(Addr)) want_granted_op);
|
||||
function TestCase testCase(String name,
|
||||
Maybe#(MemArbiterWrite#(Addr)) cpu,
|
||||
Maybe#(MemArbiterWrite#(Addr)) debugger,
|
||||
Maybe#(Addr) palette,
|
||||
Maybe#(Addr) tile1,
|
||||
Maybe#(Addr) tile2,
|
||||
Maybe#(Addr) sprite,
|
||||
Integer portA,
|
||||
Integer portB);
|
||||
return TestCase{
|
||||
name: name,
|
||||
reqs: reqs,
|
||||
conflict: conflict,
|
||||
want_grants: want_grants,
|
||||
want_granted_op: want_granted_op
|
||||
cpu: cpu,
|
||||
debugger: debugger,
|
||||
palette: palette,
|
||||
tile1: tile1,
|
||||
tile2: tile2,
|
||||
sprite: sprite,
|
||||
want: grant(portA, portB)
|
||||
};
|
||||
endfunction
|
||||
|
||||
interface TB;
|
||||
method Action start();
|
||||
(* always_ready *)
|
||||
method Bool done();
|
||||
endinterface
|
||||
module mkTB();
|
||||
Vector#(29, TestCase) tests = vec(
|
||||
testCase("All idle",
|
||||
idle, idle, idle,
|
||||
idle, idle, idle,
|
||||
-1, -1),
|
||||
|
||||
module mkArbiterTB(MemArbiter#(n, Addr) dut, Vector#(m, TestCase#(n)) tests, TB ifc);
|
||||
let cycles <- mkCycleCounter();
|
||||
// Single client accesses at a time
|
||||
testCase("CPU read", rwRead(1), idle, idle,
|
||||
idle, idle, idle,
|
||||
0, -1),
|
||||
testCase("CPU write", rwWrite(1), idle, idle,
|
||||
idle, idle, idle,
|
||||
0, -1),
|
||||
testCase("Debugger read",
|
||||
idle, rwRead(1), idle,
|
||||
idle, idle, idle,
|
||||
1, -1),
|
||||
testCase("Debugger write",
|
||||
idle, rwWrite(1), idle,
|
||||
idle, idle, idle,
|
||||
1, -1),
|
||||
testCase("Palette read",
|
||||
idle, idle, read(1),
|
||||
idle, idle, idle,
|
||||
2, -1),
|
||||
testCase("Tile1 read",
|
||||
idle, idle, idle,
|
||||
read(1), idle, idle,
|
||||
-1, 0),
|
||||
testCase("Tile2 read",
|
||||
idle, idle, idle,
|
||||
idle, read(1), idle,
|
||||
-1, 1),
|
||||
testCase("Sprite read",
|
||||
idle, idle, idle,
|
||||
idle, idle, read(1),
|
||||
-1, 2),
|
||||
|
||||
Reg#(Bit#(TLog#(m))) idx <- mkReg(0);
|
||||
Reg#(Bool) running <- mkReg(False);
|
||||
// Strict priority on port A
|
||||
testCase("CPU + Debugger + Palette",
|
||||
rwRead(1), rwRead(2), read(3),
|
||||
idle, idle, idle,
|
||||
0, -1),
|
||||
testCase("CPU + Palette",
|
||||
rwRead(1), idle, read(3),
|
||||
idle, idle, idle,
|
||||
0, -1),
|
||||
testCase("Debugger + Palette",
|
||||
idle, rwRead(2), read(3),
|
||||
idle, idle, idle,
|
||||
1, -1),
|
||||
|
||||
for (Integer i=0; i<valueOf(n); i=i+1) begin
|
||||
rule request (running && isValid(tests[idx].reqs[i]));
|
||||
dut.ports[i].request(validValue(tests[idx].reqs[i]));
|
||||
endrule
|
||||
end
|
||||
// Round-robin on port B
|
||||
testCase("Sprite read", // to reset round robin
|
||||
idle, idle, idle,
|
||||
idle, idle, read(1),
|
||||
-1, 2),
|
||||
testCase("Tile1 + Tile2 + Sprite",
|
||||
idle, idle, idle,
|
||||
read(1), read(2), read(3),
|
||||
-1, 0),
|
||||
testCase("Tile1 + Tile2 + Sprite",
|
||||
idle, idle, idle,
|
||||
read(1), read(2), read(3),
|
||||
-1, 1),
|
||||
testCase("Tile1 + Tile2 + Sprite",
|
||||
idle, idle, idle,
|
||||
read(1), read(2), read(3),
|
||||
-1, 2),
|
||||
testCase("Tile1 + Tile2 + Sprite",
|
||||
idle, idle, idle,
|
||||
read(1), read(2), read(3),
|
||||
-1, 0),
|
||||
testCase("Tile1 + Sprite",
|
||||
idle, idle, idle,
|
||||
read(1), idle, read(3),
|
||||
-1, 2),
|
||||
testCase("Tile2 + Sprite",
|
||||
idle, idle, idle,
|
||||
idle, read(2), read(3),
|
||||
-1, 1),
|
||||
testCase("Tile2 + Sprite",
|
||||
idle, idle, idle,
|
||||
idle, read(2), read(3),
|
||||
-1, 2),
|
||||
|
||||
// Inter-port conflicts
|
||||
testCase("Read/read, no conflict",
|
||||
rwRead(0), idle, idle,
|
||||
read(0), idle, idle,
|
||||
0, 0),
|
||||
testCase("Write/read, no conflict",
|
||||
rwWrite(1), idle, idle,
|
||||
read(0), idle, idle,
|
||||
0, 0),
|
||||
testCase("Tile1 write conflict",
|
||||
rwWrite(0), idle, idle,
|
||||
read(0), idle, idle,
|
||||
0, -1),
|
||||
testCase("Tile2 write conflict",
|
||||
rwWrite(0), idle, idle,
|
||||
idle, read(0), idle,
|
||||
0, -1),
|
||||
testCase("Sprite write conflict",
|
||||
rwWrite(0), idle, idle,
|
||||
idle, idle, read(0),
|
||||
0, -1),
|
||||
testCase("Tile1 write conflict with debugger",
|
||||
idle, rwWrite(0), idle,
|
||||
read(0), idle, idle,
|
||||
1, -1),
|
||||
testCase("Sprite read", // to reset round robin
|
||||
idle, idle, idle,
|
||||
idle, idle, read(1),
|
||||
-1, 2),
|
||||
testCase("CPU write conflict, other port feasible",
|
||||
rwWrite(0), idle, idle,
|
||||
read(0), read(1), idle,
|
||||
0, 1),
|
||||
testCase("CPU write conflict, conflict resolved",
|
||||
idle, idle, idle,
|
||||
read(0), idle, idle,
|
||||
-1, 0));
|
||||
|
||||
MemArbiter#(Addr) dut <- mkMemArbiter();
|
||||
|
||||
Reg#(UInt#(32)) idx <- mkReg(0);
|
||||
|
||||
rule display_test (idx == 0);
|
||||
$display("RUN TestMemArbiter");
|
||||
endrule
|
||||
|
||||
(* no_implicit_conditions, fire_when_enabled *)
|
||||
rule forbid (running && isValid(tests[idx].conflict));
|
||||
dut.conflict(validValue(tests[idx].conflict));
|
||||
rule input_cpu (tests[idx].cpu matches tagged Valid .req);
|
||||
dut.cpu.request(req);
|
||||
endrule
|
||||
|
||||
Wire#(Maybe#(MemArbiterOp#(Addr))) got_granted_op <- mkDWire(tagged Invalid);
|
||||
|
||||
(* fire_when_enabled *)
|
||||
rule collect_granted_op (running);
|
||||
got_granted_op <= tagged Valid dut.granted_op();
|
||||
(* no_implicit_conditions, fire_when_enabled *)
|
||||
rule input_debugger (tests[idx].debugger matches tagged Valid .req);
|
||||
dut.debugger.request(req);
|
||||
endrule
|
||||
|
||||
function Fmt req_s(Maybe#(MemArbiterOp#(Addr)) v);
|
||||
(* no_implicit_conditions, fire_when_enabled *)
|
||||
rule input_palette (tests[idx].palette matches tagged Valid .addr);
|
||||
dut.palette.request(addr);
|
||||
endrule
|
||||
|
||||
(* no_implicit_conditions, fire_when_enabled *)
|
||||
rule input_tile1 (tests[idx].tile1 matches tagged Valid .addr);
|
||||
dut.tile1.request(addr);
|
||||
endrule
|
||||
|
||||
(* no_implicit_conditions, fire_when_enabled *)
|
||||
rule input_tile2 (tests[idx].tile2 matches tagged Valid .addr);
|
||||
dut.tile2.request(addr);
|
||||
endrule
|
||||
|
||||
(* no_implicit_conditions, fire_when_enabled *)
|
||||
rule input_sprite (tests[idx].sprite matches tagged Valid .addr);
|
||||
dut.sprite.request(addr);
|
||||
endrule
|
||||
|
||||
function Fmt rw_str(Maybe#(MemArbiterWrite#(Addr)) v);
|
||||
case (v) matches
|
||||
tagged Invalid: return $format("Idle");
|
||||
tagged Valid .req &&& req.write: return $format("Write(%0d)", req.addr);
|
||||
tagged Valid .req: return $format("Read(%0d)", req.addr);
|
||||
tagged Valid .req: begin
|
||||
if (req.write)
|
||||
return $format("Write(%0d)", req.addr);
|
||||
else
|
||||
return $format("Read(%0d) ", req.addr);
|
||||
end
|
||||
tagged Invalid: return $format("Idle ");
|
||||
endcase
|
||||
endfunction
|
||||
|
||||
function Fmt ro_str(Maybe#(Addr) v);
|
||||
case (v) matches
|
||||
tagged Valid .addr: return $format("Read(%0d) ", addr);
|
||||
tagged Invalid: return $format("Idle ");
|
||||
endcase
|
||||
endfunction
|
||||
|
||||
(* no_implicit_conditions, fire_when_enabled *)
|
||||
rule check (running);
|
||||
rule check_grants;
|
||||
Vector#(6, Bool) gotVec = newVector;
|
||||
gotVec[0] = dut.cpu.grant();
|
||||
gotVec[1] = dut.debugger.grant();
|
||||
gotVec[2] = dut.palette.grant();
|
||||
gotVec[3] = dut.tile1.grant();
|
||||
gotVec[4] = dut.tile2.grant();
|
||||
gotVec[5] = dut.sprite.grant();
|
||||
|
||||
let test = tests[idx];
|
||||
let reqs = test.reqs;
|
||||
let want_grants = test.want_grants;
|
||||
let want_granted_op = test.want_granted_op;
|
||||
Vector#(n, Bool) got_grants = newVector;
|
||||
for (Integer i=0; i<valueOf(n); i=i+1)
|
||||
got_grants[i] = dut.ports[i].grant();
|
||||
let got = pack(reverse(gotVec));
|
||||
let want = pack(reverse(test.want));
|
||||
|
||||
$display("RUN %s (%0d)", tests[idx].name, idx);
|
||||
if (got_grants != want_grants || got_granted_op != want_granted_op) begin
|
||||
$display("input:");
|
||||
for (Integer i=0; i<valueOf(n); i=i+1)
|
||||
$display(" ", $format("%0d", i), ": ", req_s(reqs[i]));
|
||||
$display(" conflict: ", fshow(test.conflict));
|
||||
|
||||
$display(" output:");
|
||||
$display(" grants: ", fshow(got_grants));
|
||||
$display(" granted: ", fshow(got_granted_op));
|
||||
|
||||
$display(" want grants: ", fshow(tests[idx].want_grants));
|
||||
$display(" want granted: ", fshow(want_granted_op));
|
||||
dynamicAssert(False, "wrong arbiter output");
|
||||
$display("RUN %s (%0d)", test.name, idx+1);
|
||||
if (got != want) begin
|
||||
$display(" input: ",
|
||||
"0:", rw_str(test.cpu), " 1:", rw_str(test.debugger), " 2:", ro_str(test.palette),
|
||||
" 3:", ro_str(test.tile1), " 4:", ro_str(test.tile2), " 5:", ro_str(test.sprite));
|
||||
$display(" got : %03b %03b", got[5:3], got[2:0]);
|
||||
$display(" want : %03b %03b", want[5:3], want[2:0]);
|
||||
dynamicAssert(got == want, "wrong arbiter output");
|
||||
end
|
||||
|
||||
dynamicAssert(cycles == 1, "arbiter took more than 0 cycles");
|
||||
|
||||
$display("OK %s", tests[idx].name);
|
||||
|
||||
cycles.reset();
|
||||
if (idx == fromInteger(valueOf(m)-1))
|
||||
running <= False;
|
||||
else
|
||||
idx <= idx+1;
|
||||
$display("OK %s", test.name);
|
||||
endrule
|
||||
|
||||
method Action start() if (!running && idx == 0);
|
||||
cycles.reset();
|
||||
running <= True;
|
||||
endmethod
|
||||
|
||||
method Bool done();
|
||||
return !running && idx != 0;
|
||||
endmethod
|
||||
endmodule
|
||||
|
||||
module mkTB(Empty);
|
||||
///////////////////////////////
|
||||
// Strict arbiter
|
||||
|
||||
let strictTests = vec(
|
||||
// Simple grants
|
||||
testCase("All idle",
|
||||
vec(idle, idle, idle), noConflict,
|
||||
noGrant, noConflict),
|
||||
testCase("Port 0 read",
|
||||
vec(read(1), idle, idle), noConflict,
|
||||
grant(0), read(1)),
|
||||
testCase("Port 0 write",
|
||||
vec(write(1), idle, idle), noConflict,
|
||||
grant(0), write(1)),
|
||||
testCase("Port 1 read",
|
||||
vec(idle, read(1), idle), noConflict,
|
||||
grant(1), read(1)),
|
||||
testCase("Port 1 write",
|
||||
vec(idle, write(1), idle), noConflict,
|
||||
grant(1), write(1)),
|
||||
testCase("Port 2 read",
|
||||
vec(idle, idle, read(1)), noConflict,
|
||||
grant(2), read(1)),
|
||||
testCase("Port 2 write",
|
||||
vec(idle, idle, write(1)), noConflict,
|
||||
grant(2), write(1)),
|
||||
|
||||
// Priorities
|
||||
testCase("Port 0+1",
|
||||
vec(read(1), read(2), idle), noConflict,
|
||||
grant(0), read(1)),
|
||||
testCase("Port 0+2",
|
||||
vec(read(1), idle, read(2)), noConflict,
|
||||
grant(0), read(1)),
|
||||
testCase("Port 1+2",
|
||||
vec(idle, read(1), read(2)), noConflict,
|
||||
grant(1), read(1)),
|
||||
testCase("Port 0+1+2",
|
||||
vec(read(1), read(2), read(3)), noConflict,
|
||||
grant(0), read(1)),
|
||||
testCase("Port 0+1+2, overruled writes",
|
||||
vec(read(1), write(1), write(2)), noConflict,
|
||||
grant(0), read(1)),
|
||||
|
||||
// Forbidden addrs
|
||||
testCase("Port 0 read-write denied",
|
||||
vec(read(1), read(2), idle), write(1),
|
||||
grant(1), read(2)),
|
||||
testCase("Port 0 write-write denied",
|
||||
vec(write(1), read(2), idle), write(1),
|
||||
grant(1), read(2)),
|
||||
testCase("Port 0 write-read denied",
|
||||
vec(write(1), read(2), idle), read(1),
|
||||
grant(1), read(2)),
|
||||
testCase("Port 0 no addr match",
|
||||
vec(write(2), idle, idle), write(1),
|
||||
grant(0), write(2)),
|
||||
testCase("Port 0 denied, no alternatives",
|
||||
vec(write(1), idle, idle), write(1),
|
||||
noGrant, noConflict)
|
||||
);
|
||||
MemArbiter#(3, Addr) strict <- mkPriorityMemArbiter();
|
||||
let strictTB <- mkArbiterTB(strict, strictTests);
|
||||
|
||||
///////////////////////////////
|
||||
// Round-robin arbiter
|
||||
let rrTests = vec(
|
||||
// Simple grants
|
||||
testCase("All idle",
|
||||
vec(idle, idle, idle, idle), noConflict,
|
||||
noGrant, noConflict),
|
||||
testCase("Port 0 read",
|
||||
vec(read(1), idle, idle, idle), noConflict,
|
||||
grant(0), read(1)),
|
||||
testCase("Port 0 write",
|
||||
vec(write(1), idle, idle, idle), noConflict,
|
||||
grant(0), write(1)),
|
||||
testCase("Port 1 read",
|
||||
vec(idle, read(1), idle, idle), noConflict,
|
||||
grant(1), read(1)),
|
||||
testCase("Port 1 write",
|
||||
vec(idle, write(1), idle, idle), noConflict,
|
||||
grant(1), write(1)),
|
||||
testCase("Port 2 read",
|
||||
vec(idle, idle, read(1), idle), noConflict,
|
||||
grant(2), read(1)),
|
||||
testCase("Port 2 write",
|
||||
vec(idle, idle, write(1), idle), noConflict,
|
||||
grant(2), write(1)),
|
||||
testCase("Port 3 read",
|
||||
vec(idle, idle, idle, read(1)), noConflict,
|
||||
grant(3), read(1)),
|
||||
testCase("Port 3 write",
|
||||
vec(idle, idle, idle, write(1)), noConflict,
|
||||
grant(3), write(1)),
|
||||
|
||||
// Priorities
|
||||
testCase("Port 3 to reset RR",
|
||||
vec(idle, idle, idle, read(1)), noConflict,
|
||||
grant(3), read(1)),
|
||||
testCase("Port 0+1 #1",
|
||||
vec(read(1), read(2), idle, idle), noConflict,
|
||||
grant(0), read(1)),
|
||||
testCase("Port 0+1 #2",
|
||||
vec(read(1), read(2), idle, idle), noConflict,
|
||||
grant(1), read(2)),
|
||||
testCase("Port 0+1 #3",
|
||||
vec(read(1), read(2), idle, idle), noConflict,
|
||||
grant(0), read(1)),
|
||||
testCase("Port 0+2 #1",
|
||||
vec(read(1), idle, read(2), idle), noConflict,
|
||||
grant(2), read(2)),
|
||||
testCase("Port 0+2 #2",
|
||||
vec(read(1), idle, read(2), idle), noConflict,
|
||||
grant(0), read(1)),
|
||||
testCase("Port 0+1+2+3 #1",
|
||||
vec(read(1), read(2), read(3), read(4)), noConflict,
|
||||
grant(1), read(2)),
|
||||
testCase("Port 0+1+2+3 #2",
|
||||
vec(read(1), read(2), read(3), read(4)), noConflict,
|
||||
grant(2), read(3)),
|
||||
testCase("Port 0+1+2+3 #3",
|
||||
vec(read(1), read(2), read(3), read(4)), noConflict,
|
||||
grant(3), read(4)),
|
||||
testCase("Port 0+1+2+3 #4",
|
||||
vec(read(1), read(2), read(3), read(4)), noConflict,
|
||||
grant(0), read(1)),
|
||||
testCase("Port 0+1+2+3 #5",
|
||||
vec(read(1), read(2), read(3), read(4)), noConflict,
|
||||
grant(1), read(2)),
|
||||
|
||||
// Forbidden addrs
|
||||
testCase("Port 3 to reset RR",
|
||||
vec(idle, idle, idle, read(1)), noConflict,
|
||||
grant(3), read(1)),
|
||||
testCase("RR with denied writes #1",
|
||||
vec(read(1), write(2), read(3), read(4)), write(3),
|
||||
grant(0), read(1)),
|
||||
testCase("RR with denied writes #2",
|
||||
vec(read(1), write(2), read(3), read(4)), write(3),
|
||||
grant(1), write(2)),
|
||||
testCase("RR with denied writes #3",
|
||||
vec(read(1), write(2), read(3), read(4)), write(3),
|
||||
grant(3), read(4)),
|
||||
testCase("RR with denied writes #4",
|
||||
vec(read(1), write(2), read(3), read(4)), write(3),
|
||||
grant(0), read(1)),
|
||||
testCase("RR with denied writes #5",
|
||||
vec(read(1), write(2), read(3), read(4)), write(3),
|
||||
grant(1), write(2))
|
||||
);
|
||||
MemArbiter#(4, Addr) rr <- mkRoundRobinMemArbiter();
|
||||
let rrTB <- mkArbiterTB(rr, rrTests);
|
||||
|
||||
runTest(100,
|
||||
mkTest("MemArbiter", seq
|
||||
mkTest("MemArbiter/Strict", seq
|
||||
strictTB.start();
|
||||
await(strictTB.done);
|
||||
endseq);
|
||||
mkTest("MemArbiter/RoundRobin", seq
|
||||
rrTB.start();
|
||||
await(rrTB.done);
|
||||
endseq);
|
||||
endseq));
|
||||
(* no_implicit_conditions, fire_when_enabled *)
|
||||
rule advance_test;
|
||||
let next = idx+1;
|
||||
let max = fromInteger(arrayLength(vectorToArray(tests)));
|
||||
if (next == max) begin
|
||||
$display("OK TestMemArbiter");
|
||||
$finish;
|
||||
end
|
||||
else
|
||||
idx <= next;
|
||||
endrule
|
||||
endmodule
|
||||
|
||||
endpackage
|
||||
|
|
|
|||
|
|
@ -1,6 +1,5 @@
|
|||
package VRAMCore;
|
||||
package VRAM;
|
||||
|
||||
import Connectable::*;
|
||||
import GetPut::*;
|
||||
import ClientServer::*;
|
||||
import DReg::*;
|
||||
|
|
@ -16,12 +15,11 @@ import ECP5_RAM::*;
|
|||
|
||||
export VRAMAddr;
|
||||
export VRAMData;
|
||||
export mkVRAM;
|
||||
export VRAMRequest;
|
||||
export VRAMResponse;
|
||||
export VRAMClient;
|
||||
export VRAMServer;
|
||||
export VRAMCore;
|
||||
export mkVRAMCore;
|
||||
export VRAM;
|
||||
|
||||
typedef Bit#(8) VRAMData;
|
||||
|
||||
|
|
@ -135,30 +133,30 @@ typedef struct {
|
|||
typedef Server#(VRAMRequest, VRAMResponse) VRAMServer;
|
||||
typedef Client#(VRAMRequest, VRAMResponse) VRAMClient;
|
||||
|
||||
interface VRAMCore;
|
||||
interface VRAM;
|
||||
interface VRAMServer portA;
|
||||
interface VRAMServer portB;
|
||||
endinterface
|
||||
|
||||
// mkVRAMCore creates a dual port VRAM of the specified size, using
|
||||
// ECP5 EBR memory primitives. The memory size must be a multiple of
|
||||
// 4KiB, with a maximum of 128KiB.
|
||||
// mkVRAM creates a dual port VRAM of the specified size, using ECP5
|
||||
// EBR memory primitives. The memory size must be a multiple of 4KiB,
|
||||
// with a maximum of 128KiB.
|
||||
//
|
||||
// The returned VRAMCore servers implement flow control. As long as
|
||||
// The returned VRAM servers implement flow control. As long as
|
||||
// responses are processed as soon as they're available, each port can
|
||||
// process one memory operation per cycle.
|
||||
//
|
||||
// The VRAMCore does not prevent write-write or write-read conflicts
|
||||
// The VRAM does not prevent write-write or write-read conflicts
|
||||
// between the ports. The outcome of a simultaneous write to the same
|
||||
// address is unspecified, as is the read output in a simultaneous
|
||||
// read and write of the same address. The caller must use external
|
||||
// arbitration to avoid such accesses.
|
||||
module mkVRAMCore(Integer num_kilobytes, VRAMCore ifc);
|
||||
module mkVRAM(Integer num_kilobytes, VRAM ifc);
|
||||
if (num_kilobytes > 128)
|
||||
error("maximum VRAMCore size is 128KiB");
|
||||
error("maximum VRAM size is 128KiB");
|
||||
let num_bytes = num_kilobytes*1024;
|
||||
if (num_bytes % 4096 != 0)
|
||||
error("VRAMCore must be a multiple of 4096b");
|
||||
error("VRAM must be a multiple of 4096b");
|
||||
let num_byterams = num_bytes/4096;
|
||||
let num_arrays = ceil(fromInteger(num_byterams) / 8);
|
||||
|
||||
Loading…
Reference in New Issue