Compare commits
No commits in common. "e57f7e05b097cd2710dfeda6ee524476a059fd51" and "1ccd1b0072fdee2d43499b35a84360f532bd6b6d" have entirely different histories.
e57f7e05b0
...
1ccd1b0072
73
.svlint.toml
73
.svlint.toml
|
|
@ -1,73 +0,0 @@
|
||||||
syntaxrules.blocking_assignment_in_always_ff = true
|
|
||||||
syntaxrules.blocking_assignment_in_always_latch = true
|
|
||||||
syntaxrules.non_blocking_assignment_in_always_comb = true
|
|
||||||
syntaxrules.case_default = true
|
|
||||||
syntaxrules.enum_with_type = true
|
|
||||||
syntaxrules.function_with_automatic = true
|
|
||||||
syntaxrules.keyword_forbidden_priority = true
|
|
||||||
syntaxrules.keyword_forbidden_unique = true
|
|
||||||
syntaxrules.keyword_forbidden_unique0 = true
|
|
||||||
syntaxrules.operator_case_equality = true
|
|
||||||
syntaxrules.procedural_continuous_assignment = true
|
|
||||||
syntaxrules.action_block_with_side_effect = true
|
|
||||||
syntaxrules.default_nettype_none = true
|
|
||||||
syntaxrules.function_same_as_system_function = true
|
|
||||||
syntaxrules.keyword_forbidden_always = true
|
|
||||||
syntaxrules.keyword_forbidden_wire_reg = true
|
|
||||||
syntaxrules.module_nonansi_forbidden = true
|
|
||||||
syntaxrules.generate_case_with_label = true
|
|
||||||
syntaxrules.generate_for_with_label = true
|
|
||||||
syntaxrules.generate_if_with_label = true
|
|
||||||
syntaxrules.localparam_type_twostate = true
|
|
||||||
syntaxrules.parameter_type_twostate = true
|
|
||||||
syntaxrules.localparam_explicit_type = true
|
|
||||||
syntaxrules.parameter_explicit_type = true
|
|
||||||
syntaxrules.parameter_default_value = true
|
|
||||||
syntaxrules.parameter_in_generate = true
|
|
||||||
syntaxrules.parameter_in_package = true
|
|
||||||
syntaxrules.genvar_declaration_in_loop = true
|
|
||||||
syntaxrules.genvar_declaration_out_loop = false
|
|
||||||
syntaxrules.keyword_forbidden_generate = true
|
|
||||||
syntaxrules.keyword_required_generate = false
|
|
||||||
syntaxrules.explicit_case_default = true
|
|
||||||
syntaxrules.explicit_if_else = true
|
|
||||||
syntaxrules.loop_statement_in_always_comb = true
|
|
||||||
syntaxrules.loop_statement_in_always_ff = true
|
|
||||||
syntaxrules.loop_statement_in_always_latch = true
|
|
||||||
syntaxrules.sequential_block_in_always_comb = true
|
|
||||||
syntaxrules.sequential_block_in_always_ff = true
|
|
||||||
syntaxrules.sequential_block_in_always_latch = true
|
|
||||||
syntaxrules.multiline_for_begin = true
|
|
||||||
syntaxrules.multiline_if_begin = true
|
|
||||||
syntaxrules.inout_with_tri = true
|
|
||||||
syntaxrules.input_with_var = true
|
|
||||||
syntaxrules.output_with_var = true
|
|
||||||
syntaxrules.interface_port_with_modport = true
|
|
||||||
|
|
||||||
textrules.style_textwidth = false
|
|
||||||
textrules.style_semicolon = true
|
|
||||||
option.indent = 2
|
|
||||||
syntaxrules.tab_character = true
|
|
||||||
syntaxrules.style_indent = true
|
|
||||||
syntaxrules.style_trailingwhitespace = true
|
|
||||||
textrules.style_directives = true
|
|
||||||
syntaxrules.style_operator_arithmetic = true
|
|
||||||
syntaxrules.style_operator_boolean = true
|
|
||||||
syntaxrules.style_operator_integer = true
|
|
||||||
syntaxrules.style_operator_unary = true
|
|
||||||
syntaxrules.style_operator_arithmetic_leading_space = true
|
|
||||||
syntaxrules.style_operator_boolean_leading_space = true
|
|
||||||
syntaxrules.style_operator_integer_leading_space = true
|
|
||||||
|
|
||||||
syntaxrules.style_keyword_0or1space = true
|
|
||||||
syntaxrules.style_keyword_0space = true
|
|
||||||
syntaxrules.style_keyword_1or2space = true
|
|
||||||
syntaxrules.style_keyword_1space = false
|
|
||||||
syntaxrules.style_keyword_construct = true
|
|
||||||
syntaxrules.style_keyword_datatype = false # Overly restrictive.
|
|
||||||
syntaxrules.style_keyword_end = true
|
|
||||||
syntaxrules.style_keyword_maybelabel = true
|
|
||||||
syntaxrules.style_keyword_new = true
|
|
||||||
syntaxrules.style_keyword_newline = true
|
|
||||||
#syntaxrules.style_commaleading = true
|
|
||||||
syntaxrules.eventlist_or = true
|
|
||||||
|
|
@ -2,46 +2,25 @@ package Top;
|
||||||
|
|
||||||
import ECP5_RAM::*;
|
import ECP5_RAM::*;
|
||||||
|
|
||||||
(* always_enabled *)
|
//(* always_enabled *)
|
||||||
interface Top;
|
interface Top;
|
||||||
(* prefix="" *)
|
interface EBRPort#(Bit#(12), Bit#(4)) ram1;
|
||||||
method Action putA((* port="adc_miso" *) Bool write, (* port="btn" *)Bit#(4) addr, (* port="sd_d" *) Bit#(4) data);
|
interface EBRPort#(Bit#(14), Bit#(1)) ram2;
|
||||||
(* prefix="" *)
|
//interface EBRPort#(void, void) ram2;
|
||||||
method Action putB((* port="flash_csn" *) Bool write, (* port="audio_l" *) Bit#(4) addr, (* port="audio_r" *) Bit#(4) data);
|
|
||||||
(* result="led" *)
|
|
||||||
method Bit#(8) read();
|
|
||||||
//interface EBRPort#(Bit#(12), Bit#(4)) ram1;
|
|
||||||
//interface EBRPort#(Bit#(12), Bit#(4)) ram2;
|
|
||||||
endinterface
|
endinterface
|
||||||
|
|
||||||
(* synthesize,clock_prefix="clk_25mhz",reset_prefix="audio_v" *)
|
(* synthesize *)
|
||||||
module mkTop(Top ifc);
|
module mkTop(Clock clk2, Reset rst2, Top ifc);
|
||||||
EBRPortConfig cfgA = defaultValue;
|
EBRPortConfig cfgA = defaultValue;
|
||||||
cfgA.write_mode = Normal;
|
cfgA.write_mode = Normal;
|
||||||
cfgA.chip_select_addr = 5;
|
|
||||||
EBRPortConfig cfgB = defaultValue;
|
EBRPortConfig cfgB = defaultValue;
|
||||||
// cfgB.clk = tagged Valid clk2;
|
cfgB.clk = tagged Valid clk2;
|
||||||
// cfgB.rstN = tagged Valid rst2;
|
cfgB.rstN = tagged Valid rst2;
|
||||||
cfgB.register_output = True;
|
cfgB.register_output = True;
|
||||||
let r <- mkEBR(cfgA, cfgB);
|
let r <- mkEBR(cfgA, cfgB);
|
||||||
|
|
||||||
Wire#(Bit#(8)) out <- mkDWire(0);
|
interface EBRPort ram1 = r.portA;
|
||||||
|
interface EBRPort ram2 = r.portB;
|
||||||
rule collect_output;
|
|
||||||
out <= {r.portA.read, r.portB.read};
|
|
||||||
endrule
|
|
||||||
|
|
||||||
method Action putA(Bool write, Bit#(4) addr, Bit#(4) data);
|
|
||||||
r.portA.put(0, write, addr, data);
|
|
||||||
endmethod
|
|
||||||
method Action putB(Bool write, Bit#(4) addr, Bit#(4) data);
|
|
||||||
r.portB.put(0, write, addr, data);
|
|
||||||
endmethod
|
|
||||||
method Bit#(8) read();
|
|
||||||
return out;
|
|
||||||
endmethod
|
|
||||||
//interface EBRPort ram1 = r.portA;
|
|
||||||
//interface EBRPort ram2 = r.portB;
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
endpackage
|
endpackage
|
||||||
|
|
|
||||||
|
|
@ -1,598 +0,0 @@
|
||||||
BLOCK RESETPATHS;
|
|
||||||
BLOCK ASYNCPATHS;
|
|
||||||
## ULX3S v2.x.x and v3.0.x
|
|
||||||
|
|
||||||
# The clock "usb" and "gpdi" sheet
|
|
||||||
LOCATE COMP "clk_25mhz" SITE "G2";
|
|
||||||
IOBUF PORT "clk_25mhz" PULLMODE=NONE IO_TYPE=LVCMOS33;
|
|
||||||
FREQUENCY PORT "clk_25mhz" 25 MHZ;
|
|
||||||
|
|
||||||
# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash
|
|
||||||
# write to FLASH possible any time from JTAG:
|
|
||||||
SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE;
|
|
||||||
# write to FLASH possible from user bitstream:
|
|
||||||
# SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE;
|
|
||||||
|
|
||||||
## USBSERIAL FTDI-FPGA serial port "usb" sheet
|
|
||||||
LOCATE COMP "ftdi_rxd" SITE "L4"; # FPGA transmits to ftdi
|
|
||||||
LOCATE COMP "ftdi_txd" SITE "M1"; # FPGA receives from ftdi
|
|
||||||
LOCATE COMP "ftdi_nrts" SITE "M3"; # FPGA receives
|
|
||||||
LOCATE COMP "ftdi_ndtr" SITE "N1"; # FPGA receives
|
|
||||||
LOCATE COMP "ftdi_txden" SITE "L3"; # FPGA receives
|
|
||||||
IOBUF PORT "ftdi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "ftdi_txd" PULLMODE=UP IO_TYPE=LVCMOS33;
|
|
||||||
IOBUF PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33;
|
|
||||||
IOBUF PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33;
|
|
||||||
IOBUF PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33;
|
|
||||||
|
|
||||||
## LED indicators "blinkey" and "gpio" sheet
|
|
||||||
LOCATE COMP "led[7]" SITE "H3";
|
|
||||||
LOCATE COMP "led[6]" SITE "E1";
|
|
||||||
LOCATE COMP "led[5]" SITE "E2";
|
|
||||||
LOCATE COMP "led[4]" SITE "D1";
|
|
||||||
LOCATE COMP "led[3]" SITE "D2";
|
|
||||||
LOCATE COMP "led[2]" SITE "C1";
|
|
||||||
LOCATE COMP "led[1]" SITE "C2";
|
|
||||||
LOCATE COMP "led[0]" SITE "B2";
|
|
||||||
IOBUF PORT "led[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "led[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "led[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "led[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "led[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "led[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "led[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "led[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
|
|
||||||
## Pushbuttons "blinkey", "flash", "power", "gpdi" sheet
|
|
||||||
LOCATE COMP "btn[0]" SITE "D6"; # BTN_PWRn (inverted logic)
|
|
||||||
LOCATE COMP "btn[1]" SITE "R1"; # FIRE1
|
|
||||||
LOCATE COMP "btn[2]" SITE "T1"; # FIRE2
|
|
||||||
LOCATE COMP "btn[3]" SITE "R18"; # UP W1->R18
|
|
||||||
LOCATE COMP "btn[4]" SITE "V1"; # DOWN
|
|
||||||
LOCATE COMP "btn[5]" SITE "U1"; # LEFT
|
|
||||||
LOCATE COMP "btn[6]" SITE "H16"; # RIGHT Y2->H16
|
|
||||||
IOBUF PORT "btn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "btn[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "btn[4]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "btn[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "btn[6]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
|
|
||||||
## DIP switch "blinkey", "gpio" sheet
|
|
||||||
LOCATE COMP "sw[0]" SITE "E8"; # SW1
|
|
||||||
LOCATE COMP "sw[1]" SITE "D8"; # SW2
|
|
||||||
LOCATE COMP "sw[2]" SITE "D7"; # SW3
|
|
||||||
LOCATE COMP "sw[3]" SITE "E7"; # SW4
|
|
||||||
IOBUF PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
|
|
||||||
## SPI OLED DISPLAY SSD1331 (Color) or SSD1306 (B/W) "blinkey", "usb" sheet
|
|
||||||
LOCATE COMP "oled_clk" SITE "P4";
|
|
||||||
LOCATE COMP "oled_mosi" SITE "P3";
|
|
||||||
LOCATE COMP "oled_dc" SITE "P1";
|
|
||||||
LOCATE COMP "oled_resn" SITE "P2";
|
|
||||||
LOCATE COMP "oled_csn" SITE "N2";
|
|
||||||
IOBUF PORT "oled_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "oled_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "oled_dc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "oled_resn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "oled_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
|
|
||||||
## SPI Flash chip "flash" sheet
|
|
||||||
LOCATE COMP "flash_csn" SITE "R2";
|
|
||||||
LOCATE COMP "flash_clk" SITE "U3";
|
|
||||||
LOCATE COMP "flash_mosi" SITE "W2";
|
|
||||||
LOCATE COMP "flash_miso" SITE "V2";
|
|
||||||
LOCATE COMP "flash_holdn" SITE "W1";
|
|
||||||
LOCATE COMP "flash_wpn" SITE "Y2";
|
|
||||||
#LOCATE COMP "flash_csspin" SITE "AJ3";
|
|
||||||
#LOCATE COMP "flash_initn" SITE "AG4";
|
|
||||||
#LOCATE COMP "flash_done" SITE "AJ4";
|
|
||||||
#LOCATE COMP "flash_programn" SITE "AH4";
|
|
||||||
#LOCATE COMP "flash_cfg_select[0]" SITE "AM4";
|
|
||||||
#LOCATE COMP "flash_cfg_select[1]" SITE "AL4";
|
|
||||||
#LOCATE COMP "flash_cfg_select[2]" SITE "AK4";
|
|
||||||
IOBUF PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "flash_holdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "flash_wpn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
#IOBUF PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
#IOBUF PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
#IOBUF PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
#IOBUF PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
#IOBUF PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
#IOBUF PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
#IOBUF PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
|
|
||||||
## SD card "sdcard", "usb" sheet
|
|
||||||
# wifi_gpio2,4,12,13,14,15 are shared with SD card.
|
|
||||||
# If any of wifi_gpio2,4,12,13 is used in toplevel, don't use sd_d[].
|
|
||||||
# If SD is used in 1-bit SPI mode, wifi_gpio4,12 = sd_d[1,2] are free,
|
|
||||||
LOCATE COMP "sd_clk" SITE "H2"; # sd_clk WiFi_GPIO14
|
|
||||||
LOCATE COMP "sd_cmd" SITE "J1"; # sd_cmd_di (MOSI) WiFi GPIO15
|
|
||||||
LOCATE COMP "sd_d[0]" SITE "J3"; # sd_d0_do (MISO) WiFi GPIO2
|
|
||||||
LOCATE COMP "sd_d[1]" SITE "H1"; # sd_d1_irq WiFi GPIO4
|
|
||||||
LOCATE COMP "sd_d[2]" SITE "K1"; # sd_d2 WiFi_GPIO12
|
|
||||||
LOCATE COMP "sd_d[3]" SITE "K2"; # sd_d3_csn WiFi_GPIO13
|
|
||||||
LOCATE COMP "sd_wp" SITE "P5"; # not connected
|
|
||||||
LOCATE COMP "sd_cdn" SITE "N5"; # not connected
|
|
||||||
IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping without 3.3V efuse
|
|
||||||
IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
|
|
||||||
## ADC SPI (MAX11123) "analog", "ram" sheet
|
|
||||||
# input lines shared with GP,GN14-17
|
|
||||||
LOCATE COMP "adc_csn" SITE "R17";
|
|
||||||
LOCATE COMP "adc_mosi" SITE "R16";
|
|
||||||
LOCATE COMP "adc_miso" SITE "U16";
|
|
||||||
LOCATE COMP "adc_sclk" SITE "P17";
|
|
||||||
IOBUF PORT "adc_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "adc_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "adc_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "adc_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
|
|
||||||
## Audio 4-bit DAC "analog", "gpio" sheet
|
|
||||||
# output impedance: 75 ohm
|
|
||||||
# Stereo 16 ohm earphones, analog audio,
|
|
||||||
# SPDIF digital audio and composite video.
|
|
||||||
LOCATE COMP "audio_l[3]" SITE "B3"; # JACK TIP (left audio)
|
|
||||||
LOCATE COMP "audio_l[2]" SITE "C3";
|
|
||||||
LOCATE COMP "audio_l[1]" SITE "D3";
|
|
||||||
LOCATE COMP "audio_l[0]" SITE "E4";
|
|
||||||
LOCATE COMP "audio_r[3]" SITE "C5"; # JACK RING1 (right audio)
|
|
||||||
LOCATE COMP "audio_r[2]" SITE "D5";
|
|
||||||
LOCATE COMP "audio_r[1]" SITE "B5";
|
|
||||||
LOCATE COMP "audio_r[0]" SITE "A3";
|
|
||||||
LOCATE COMP "audio_v[3]" SITE "E5"; # JACK RING2 (video or digital audio)
|
|
||||||
LOCATE COMP "audio_v[2]" SITE "F5";
|
|
||||||
LOCATE COMP "audio_v[1]" SITE "F2";
|
|
||||||
LOCATE COMP "audio_v[0]" SITE "H5";
|
|
||||||
IOBUF PORT "audio_l[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
|
||||||
IOBUF PORT "audio_l[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
|
||||||
IOBUF PORT "audio_l[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
|
||||||
IOBUF PORT "audio_l[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
|
||||||
IOBUF PORT "audio_r[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
|
||||||
IOBUF PORT "audio_r[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
|
||||||
IOBUF PORT "audio_r[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
|
||||||
IOBUF PORT "audio_r[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
|
||||||
IOBUF PORT "audio_v[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
|
||||||
IOBUF PORT "audio_v[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
|
||||||
IOBUF PORT "audio_v[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
|
||||||
IOBUF PORT "audio_v[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
|
||||||
|
|
||||||
## WiFi ESP-32 "wifi", "usb", "flash" sheet
|
|
||||||
# wifi_gpio2,4,12,13,14,15 are shared with SD card.
|
|
||||||
# If any of wifi_gpio2,4,12,13 is used in toplevel, don't use sd_d[].
|
|
||||||
# If SD is used in 1-bit SPI mode, wifi_gpio4,12 = sd_d[1,2] are free,
|
|
||||||
# other pins are shared with GP/GN, and JTAG
|
|
||||||
LOCATE COMP "wifi_en" SITE "F1"; # enable/reset WiFi
|
|
||||||
LOCATE COMP "wifi_rxd" SITE "K3"; # FPGA transmits to WiFi
|
|
||||||
LOCATE COMP "wifi_txd" SITE "K4"; # FPGA receives from WiFi
|
|
||||||
LOCATE COMP "wifi_gpio0" SITE "L2";
|
|
||||||
LOCATE COMP "wifi_gpio5" SITE "N4"; # WIFI LED
|
|
||||||
LOCATE COMP "wifi_gpio16" SITE "L1"; # Serial1 RX
|
|
||||||
LOCATE COMP "wifi_gpio17" SITE "N3"; # Serial1 TX
|
|
||||||
# LOCATE COMP "prog_done" SITE "Y3"; # not GPIO, always active
|
|
||||||
# wifi lines shared with SD card
|
|
||||||
LOCATE COMP "wifi_gpio2" SITE "J3"; # sd_d0_do (MISO) WiFi GPIO2
|
|
||||||
LOCATE COMP "wifi_gpio4" SITE "H1"; # sd_d1_irq WiFi GPIO4
|
|
||||||
LOCATE COMP "wifi_gpio12" SITE "K1"; # sd_d2 WiFi_GPIO12
|
|
||||||
LOCATE COMP "wifi_gpio13" SITE "K2"; # sd_d3_csn WiFi_GPIO13
|
|
||||||
LOCATE COMP "wifi_gpio14" SITE "H2"; # sd_clk WiFi_GPIO14
|
|
||||||
LOCATE COMP "wifi_gpio15" SITE "J1"; # sd_cmd_di (MOSI) WiFi GPIO15
|
|
||||||
# wifi lines shared with JTAG
|
|
||||||
# LOCATE COMP "wifi_gpio21" SITE "U5"; # JTAG TMS
|
|
||||||
# LOCATE COMP "wifi_gpio18" SITE "T5"; # JTAG TCK
|
|
||||||
# LOCATE COMP "wifi_gpio23" SITE "R5"; # JTAG TDI
|
|
||||||
# LOCATE COMP "wifi_gpio19" SITE "V4"; # JTAG TDO
|
|
||||||
IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "wifi_gpio5" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; # pull down or drive 0 for esp32 programming
|
|
||||||
IOBUF PORT "wifi_gpio16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "wifi_gpio17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
# IOBUF PORT "prog_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
|
|
||||||
## PCB antenna 433 MHz (may be also used for FM) "usb" sheet
|
|
||||||
LOCATE COMP "ant_433mhz" SITE "G1";
|
|
||||||
IOBUF PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
|
|
||||||
## Second USB port "US2" going directly into FPGA "usb", "ram" sheet
|
|
||||||
LOCATE COMP "usb_fpga_dp" SITE "E16"; # single ended or differential input only
|
|
||||||
LOCATE COMP "usb_fpga_dn" SITE "F16";
|
|
||||||
IOBUF PORT "usb_fpga_dp" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16;
|
|
||||||
IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16;
|
|
||||||
LOCATE COMP "usb_fpga_bd_dp" SITE "D15"; # single-ended bidirectional
|
|
||||||
LOCATE COMP "usb_fpga_bd_dn" SITE "E15";
|
|
||||||
IOBUF PORT "usb_fpga_bd_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "usb_fpga_bd_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
LOCATE COMP "usb_fpga_pu_dp" SITE "B12"; # pull up/down control
|
|
||||||
LOCATE COMP "usb_fpga_pu_dn" SITE "C12";
|
|
||||||
IOBUF PORT "usb_fpga_pu_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
|
||||||
IOBUF PORT "usb_fpga_pu_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
|
||||||
|
|
||||||
## JTAG ESP-32 "usb" sheet
|
|
||||||
# connected to FT231X and ESP-32
|
|
||||||
# commented out because those are dedicated pins, not directly useable as GPIO
|
|
||||||
# but could be used by some vendor-specific JTAG bridging (boundary scan) module
|
|
||||||
#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI FPGA receives
|
|
||||||
#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS FPGA transmits
|
|
||||||
#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR FPGA receives
|
|
||||||
#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD FPGA receives
|
|
||||||
#IOBUF PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
#IOBUF PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
#IOBUF PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
#IOBUF PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
|
|
||||||
## SDRAM "ram" sheet
|
|
||||||
LOCATE COMP "sdram_clk" SITE "F19";
|
|
||||||
LOCATE COMP "sdram_cke" SITE "F20";
|
|
||||||
LOCATE COMP "sdram_csn" SITE "P20";
|
|
||||||
LOCATE COMP "sdram_wen" SITE "T20";
|
|
||||||
LOCATE COMP "sdram_rasn" SITE "R20";
|
|
||||||
LOCATE COMP "sdram_casn" SITE "T19";
|
|
||||||
LOCATE COMP "sdram_a[0]" SITE "M20";
|
|
||||||
LOCATE COMP "sdram_a[1]" SITE "M19";
|
|
||||||
LOCATE COMP "sdram_a[2]" SITE "L20";
|
|
||||||
LOCATE COMP "sdram_a[3]" SITE "L19";
|
|
||||||
LOCATE COMP "sdram_a[4]" SITE "K20";
|
|
||||||
LOCATE COMP "sdram_a[5]" SITE "K19";
|
|
||||||
LOCATE COMP "sdram_a[6]" SITE "K18";
|
|
||||||
LOCATE COMP "sdram_a[7]" SITE "J20";
|
|
||||||
LOCATE COMP "sdram_a[8]" SITE "J19";
|
|
||||||
LOCATE COMP "sdram_a[9]" SITE "H20";
|
|
||||||
LOCATE COMP "sdram_a[10]" SITE "N19";
|
|
||||||
LOCATE COMP "sdram_a[11]" SITE "G20";
|
|
||||||
LOCATE COMP "sdram_a[12]" SITE "G19";
|
|
||||||
LOCATE COMP "sdram_ba[0]" SITE "P19";
|
|
||||||
LOCATE COMP "sdram_ba[1]" SITE "N20";
|
|
||||||
LOCATE COMP "sdram_dqm[0]" SITE "U19";
|
|
||||||
LOCATE COMP "sdram_dqm[1]" SITE "E20";
|
|
||||||
LOCATE COMP "sdram_d[0]" SITE "J16";
|
|
||||||
LOCATE COMP "sdram_d[1]" SITE "L18";
|
|
||||||
LOCATE COMP "sdram_d[2]" SITE "M18";
|
|
||||||
LOCATE COMP "sdram_d[3]" SITE "N18";
|
|
||||||
LOCATE COMP "sdram_d[4]" SITE "P18";
|
|
||||||
LOCATE COMP "sdram_d[5]" SITE "T18";
|
|
||||||
LOCATE COMP "sdram_d[6]" SITE "T17";
|
|
||||||
LOCATE COMP "sdram_d[7]" SITE "U20";
|
|
||||||
LOCATE COMP "sdram_d[8]" SITE "E19";
|
|
||||||
LOCATE COMP "sdram_d[9]" SITE "D20";
|
|
||||||
LOCATE COMP "sdram_d[10]" SITE "D19";
|
|
||||||
LOCATE COMP "sdram_d[11]" SITE "C20";
|
|
||||||
LOCATE COMP "sdram_d[12]" SITE "E18";
|
|
||||||
LOCATE COMP "sdram_d[13]" SITE "F18";
|
|
||||||
LOCATE COMP "sdram_d[14]" SITE "J18";
|
|
||||||
LOCATE COMP "sdram_d[15]" SITE "J17";
|
|
||||||
IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
|
|
||||||
# GPDI differential interface (Video) "gpdi" sheet
|
|
||||||
LOCATE COMP "gpdi_dp[0]" SITE "A16"; # Blue +
|
|
||||||
LOCATE COMP "gpdi_dn[0]" SITE "B16"; # Blue -
|
|
||||||
LOCATE COMP "gpdi_dp[1]" SITE "A14"; # Green +
|
|
||||||
LOCATE COMP "gpdi_dn[1]" SITE "C14"; # Green -
|
|
||||||
LOCATE COMP "gpdi_dp[2]" SITE "A12"; # Red +
|
|
||||||
LOCATE COMP "gpdi_dn[2]" SITE "A13"; # Red -
|
|
||||||
LOCATE COMP "gpdi_dp[3]" SITE "A17"; # Clock +
|
|
||||||
LOCATE COMP "gpdi_dn[3]" SITE "B18"; # Clock -
|
|
||||||
LOCATE COMP "gpdi_util" SITE "A19"; # add 10k parallel to C
|
|
||||||
LOCATE COMP "gpdi_hpd" SITE "B20"; # add 549ohm parallel to C
|
|
||||||
LOCATE COMP "gpdi_cec" SITE "A18";
|
|
||||||
LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC
|
|
||||||
LOCATE COMP "gpdi_scl" SITE "E12"; # I2C shared with RTC C12->E12
|
|
||||||
IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33D DRIVE=4;
|
|
||||||
IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33D DRIVE=4;
|
|
||||||
IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33D DRIVE=4;
|
|
||||||
IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33D DRIVE=4;
|
|
||||||
IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33D DRIVE=4;
|
|
||||||
IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33D DRIVE=4;
|
|
||||||
IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33D DRIVE=4;
|
|
||||||
IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33D DRIVE=4;
|
|
||||||
IOBUF PORT "gpdi_util" IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gpdi_hpd" IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
|
|
||||||
# GPIO (default single-ended) "gpio", "ram", "gpdi" sheet
|
|
||||||
# Pins enumerated gp[0-27], gn[0-27].
|
|
||||||
# With differential mode enabled on Lattice,
|
|
||||||
# gp[] (+) are used, gn[] (-) are ignored from design
|
|
||||||
# as they handle inverted signal by default.
|
|
||||||
# To enable differential, rename LVCMOS33->LVCMOS33D
|
|
||||||
# FEMALE ANGLED (90 deg PMOD) on TOP or
|
|
||||||
# MALE VERTICAL ( 0 deg pins) on BOTTOM and flat cable
|
|
||||||
LOCATE COMP "gp[0]" SITE "B11"; # PCLK
|
|
||||||
LOCATE COMP "gn[0]" SITE "C11"; # PCLK
|
|
||||||
LOCATE COMP "gp[1]" SITE "A10"; # PCLK
|
|
||||||
LOCATE COMP "gn[1]" SITE "A11"; # PCLK
|
|
||||||
LOCATE COMP "gp[2]" SITE "A9"; # GR_PCLK
|
|
||||||
LOCATE COMP "gn[2]" SITE "B10"; # GR_PCLK
|
|
||||||
LOCATE COMP "gp[3]" SITE "B9";
|
|
||||||
LOCATE COMP "gn[3]" SITE "C10";
|
|
||||||
LOCATE COMP "gp[4]" SITE "A7";
|
|
||||||
LOCATE COMP "gn[4]" SITE "A8";
|
|
||||||
LOCATE COMP "gp[5]" SITE "C8";
|
|
||||||
LOCATE COMP "gn[5]" SITE "B8";
|
|
||||||
LOCATE COMP "gp[6]" SITE "C6";
|
|
||||||
LOCATE COMP "gn[6]" SITE "C7";
|
|
||||||
IOBUF PORT "gp[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
LOCATE COMP "gp[7]" SITE "A6";
|
|
||||||
LOCATE COMP "gn[7]" SITE "B6";
|
|
||||||
LOCATE COMP "gp[8]" SITE "A4"; # DIFF
|
|
||||||
LOCATE COMP "gn[8]" SITE "A5"; # DIFF
|
|
||||||
LOCATE COMP "gp[9]" SITE "A2"; # DIFF
|
|
||||||
LOCATE COMP "gn[9]" SITE "B1"; # DIFF
|
|
||||||
LOCATE COMP "gp[10]" SITE "C4"; # DIFF
|
|
||||||
LOCATE COMP "gn[10]" SITE "B4"; # DIFF
|
|
||||||
LOCATE COMP "gp[11]" SITE "F4"; # DIFF wifi_gpio26
|
|
||||||
LOCATE COMP "gn[11]" SITE "E3"; # DIFF wifi_gpio25
|
|
||||||
LOCATE COMP "gp[12]" SITE "G3"; # DIFF wifi_gpio33 PCLK
|
|
||||||
LOCATE COMP "gn[12]" SITE "F3"; # DIFF wifi_gpio32 PCLK
|
|
||||||
LOCATE COMP "gp[13]" SITE "H4"; # DIFF wifi_gpio35
|
|
||||||
LOCATE COMP "gn[13]" SITE "G5"; # DIFF wifi_gpio34
|
|
||||||
IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[12]" PULLMODE=NONE IO_TYPE=LVCMOS33;
|
|
||||||
FREQUENCY PORT "gn[12]" 50 MHZ;
|
|
||||||
IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
LOCATE COMP "gp[14]" SITE "U18"; # DIFF ADC AIN1
|
|
||||||
LOCATE COMP "gn[14]" SITE "U17"; # DIFF ADC AIN0
|
|
||||||
LOCATE COMP "gp[15]" SITE "N17"; # DIFF ADC AIN3
|
|
||||||
LOCATE COMP "gn[15]" SITE "P16"; # DIFF ADC AIN2
|
|
||||||
LOCATE COMP "gp[16]" SITE "N16"; # DIFF ADC AIN5
|
|
||||||
LOCATE COMP "gn[16]" SITE "M17"; # DIFF ADC AIN4
|
|
||||||
LOCATE COMP "gp[17]" SITE "L16"; # DIFF ADC AIN7 GR_PCLK
|
|
||||||
LOCATE COMP "gn[17]" SITE "L17"; # DIFF ADC AIN6
|
|
||||||
LOCATE COMP "gp[18]" SITE "H18"; # DIFF
|
|
||||||
LOCATE COMP "gn[18]" SITE "H17"; # DIFF
|
|
||||||
LOCATE COMP "gp[19]" SITE "F17"; # DIFF
|
|
||||||
LOCATE COMP "gn[19]" SITE "G18"; # DIFF
|
|
||||||
LOCATE COMP "gp[20]" SITE "D18"; # DIFF
|
|
||||||
LOCATE COMP "gn[20]" SITE "E17"; # DIFF
|
|
||||||
IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
LOCATE COMP "gp[21]" SITE "C18"; # DIFF
|
|
||||||
LOCATE COMP "gn[21]" SITE "D17"; # DIFF
|
|
||||||
LOCATE COMP "gp[22]" SITE "B15";
|
|
||||||
LOCATE COMP "gn[22]" SITE "C15";
|
|
||||||
LOCATE COMP "gp[23]" SITE "B17";
|
|
||||||
LOCATE COMP "gn[23]" SITE "C17";
|
|
||||||
LOCATE COMP "gp[24]" SITE "C16";
|
|
||||||
LOCATE COMP "gn[24]" SITE "D16";
|
|
||||||
LOCATE COMP "gp[25]" SITE "D14";
|
|
||||||
LOCATE COMP "gn[25]" SITE "E14";
|
|
||||||
LOCATE COMP "gp[26]" SITE "B13";
|
|
||||||
LOCATE COMP "gn[26]" SITE "C13";
|
|
||||||
LOCATE COMP "gp[27]" SITE "D13";
|
|
||||||
LOCATE COMP "gn[27]" SITE "E13";
|
|
||||||
IOBUF PORT "gp[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
|
|
||||||
## GPIO repeated as individual signals (non-vector)
|
|
||||||
# Allows mixed input, output, bidirectional, clock, differential
|
|
||||||
# If any of individual gp is used, then don't use gp[] vector.
|
|
||||||
# Same for gn and gn[].
|
|
||||||
# FEMALE ANGLED (90 deg PMOD) on TOP or
|
|
||||||
# MALE VERTICAL ( 0 deg pins) on BOTTOM and flat cable
|
|
||||||
LOCATE COMP "gp0" SITE "B11"; # PCLK
|
|
||||||
LOCATE COMP "gn0" SITE "C11"; # PCLK
|
|
||||||
LOCATE COMP "gp1" SITE "A10"; # PCLK
|
|
||||||
LOCATE COMP "gn1" SITE "A11"; # PCLK
|
|
||||||
LOCATE COMP "gp2" SITE "A9"; # GR_PCLK
|
|
||||||
LOCATE COMP "gn2" SITE "B10"; # GR_PCLK
|
|
||||||
LOCATE COMP "gp3" SITE "B9";
|
|
||||||
LOCATE COMP "gn3" SITE "C10";
|
|
||||||
LOCATE COMP "gp4" SITE "A7";
|
|
||||||
LOCATE COMP "gn4" SITE "A8";
|
|
||||||
LOCATE COMP "gp5" SITE "C8";
|
|
||||||
LOCATE COMP "gn5" SITE "B8";
|
|
||||||
LOCATE COMP "gp6" SITE "C6";
|
|
||||||
LOCATE COMP "gn6" SITE "C7";
|
|
||||||
IOBUF PORT "gp0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp1" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn1" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp2" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn2" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp3" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn3" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp4" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn4" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp5" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn5" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp6" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn6" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
LOCATE COMP "gp7" SITE "A6";
|
|
||||||
LOCATE COMP "gn7" SITE "B6";
|
|
||||||
LOCATE COMP "gp8" SITE "A4"; # DIFF
|
|
||||||
LOCATE COMP "gn8" SITE "A5"; # DIFF
|
|
||||||
LOCATE COMP "gp9" SITE "A2"; # DIFF
|
|
||||||
LOCATE COMP "gn9" SITE "B1"; # DIFF
|
|
||||||
LOCATE COMP "gp10" SITE "C4"; # DIFF
|
|
||||||
LOCATE COMP "gn10" SITE "B4"; # DIFF
|
|
||||||
LOCATE COMP "gp11" SITE "F4"; # DIFF wifi_gpio26
|
|
||||||
LOCATE COMP "gn11" SITE "E3"; # DIFF wifi_gpio25
|
|
||||||
LOCATE COMP "gp12" SITE "G3"; # DIFF wifi_gpio33 PCLK
|
|
||||||
LOCATE COMP "gn12" SITE "F3"; # DIFF wifi_gpio32 PCLK
|
|
||||||
LOCATE COMP "gp13" SITE "H4"; # DIFF wifi_gpio35
|
|
||||||
LOCATE COMP "gn13" SITE "G5"; # DIFF wifi_gpio34
|
|
||||||
# wifi sharing PCB v2.0.6-v3.0.8
|
|
||||||
# prior to v2.0.6 see schematics
|
|
||||||
IOBUF PORT "gp7" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn7" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp8" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn8" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp9" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn9" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp10" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn10" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp11" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn11" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp12" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn12" PULLMODE=NONE IO_TYPE=LVCMOS33;
|
|
||||||
FREQUENCY PORT "gn12" 50 MHZ;
|
|
||||||
IOBUF PORT "gp13" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn13" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
LOCATE COMP "gp14" SITE "U18"; # DIFF ADC AIN1
|
|
||||||
LOCATE COMP "gn14" SITE "U17"; # DIFF ADC AIN0
|
|
||||||
LOCATE COMP "gp15" SITE "N17"; # DIFF ADC AIN3
|
|
||||||
LOCATE COMP "gn15" SITE "P16"; # DIFF ADC AIN2
|
|
||||||
LOCATE COMP "gp16" SITE "N16"; # DIFF ADC AIN5
|
|
||||||
LOCATE COMP "gn16" SITE "M17"; # DIFF ADC AIN4
|
|
||||||
LOCATE COMP "gp17" SITE "L16"; # DIFF ADC AIN7 GR_PCLK
|
|
||||||
LOCATE COMP "gn17" SITE "L17"; # DIFF ADC AIN6
|
|
||||||
LOCATE COMP "gp18" SITE "H18"; # DIFF
|
|
||||||
LOCATE COMP "gn18" SITE "H17"; # DIFF
|
|
||||||
LOCATE COMP "gp19" SITE "F17"; # DIFF
|
|
||||||
LOCATE COMP "gn19" SITE "G18"; # DIFF
|
|
||||||
LOCATE COMP "gp20" SITE "D18"; # DIFF
|
|
||||||
LOCATE COMP "gn20" SITE "E17"; # DIFF
|
|
||||||
IOBUF PORT "gp14" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn14" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp15" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn15" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp18" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn18" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp19" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn19" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp20" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn20" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
LOCATE COMP "gp21" SITE "C18"; # DIFF
|
|
||||||
LOCATE COMP "gn21" SITE "D17"; # DIFF
|
|
||||||
LOCATE COMP "gp22" SITE "B15";
|
|
||||||
LOCATE COMP "gn22" SITE "C15";
|
|
||||||
LOCATE COMP "gp23" SITE "B17";
|
|
||||||
LOCATE COMP "gn23" SITE "C17";
|
|
||||||
LOCATE COMP "gp24" SITE "C16";
|
|
||||||
LOCATE COMP "gn24" SITE "D16";
|
|
||||||
LOCATE COMP "gp25" SITE "D14";
|
|
||||||
LOCATE COMP "gn25" SITE "E14";
|
|
||||||
LOCATE COMP "gp26" SITE "B13";
|
|
||||||
LOCATE COMP "gn26" SITE "C13";
|
|
||||||
LOCATE COMP "gp27" SITE "D13";
|
|
||||||
LOCATE COMP "gn27" SITE "E13";
|
|
||||||
IOBUF PORT "gp21" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn21" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp22" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn22" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp23" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn23" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp24" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn24" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp25" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn25" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp26" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn26" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gp27" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
IOBUF PORT "gn27" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
|
|
||||||
## PROGRAMN (reload bitstream from FLASH, exit from bootloader)
|
|
||||||
# PCB v2.0.5 and higher
|
|
||||||
LOCATE COMP "user_programn" SITE "M4";
|
|
||||||
IOBUF PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
|
|
||||||
## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5)
|
|
||||||
# on PCB v1.7 shutdown is not connected to FPGA
|
|
||||||
LOCATE COMP "shutdown" SITE "G16"; # FPGA receives
|
|
||||||
IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
|
||||||
|
|
@ -29,11 +29,7 @@
|
||||||
picocom
|
picocom
|
||||||
(python3.withPackages (py-pkgs: [
|
(python3.withPackages (py-pkgs: [
|
||||||
py-pkgs.invoke
|
py-pkgs.invoke
|
||||||
py-pkgs.distutils
|
|
||||||
py-pkgs.xdot
|
|
||||||
]))
|
]))
|
||||||
svlint
|
|
||||||
svls
|
|
||||||
symbiyosys
|
symbiyosys
|
||||||
trellis
|
trellis
|
||||||
verilator
|
verilator
|
||||||
|
|
|
||||||
|
|
@ -126,10 +126,9 @@ typedef struct {
|
||||||
// that it is less than or equal to the maximum address width that
|
// that it is less than or equal to the maximum address width that
|
||||||
// makes sense for data_width.
|
// makes sense for data_width.
|
||||||
Integer addr_width;
|
Integer addr_width;
|
||||||
// data_width is the bit width of input and output values at the
|
// data_width is the bit width of input and output values. It is
|
||||||
// primitive hardware layer. The data width exported from the
|
// always one of the valid values for the EBR primitive: 1, 2, 4, 9
|
||||||
// wrapper types can be narrower. This value is always one of the
|
// or 18.
|
||||||
// valid values for the EBR primitive: 1, 2, 4, 9 or 18.
|
|
||||||
Integer data_width;
|
Integer data_width;
|
||||||
// write_outputs_data is whether write_mode is one of the modes
|
// write_outputs_data is whether write_mode is one of the modes
|
||||||
// where write operations output a value. Modules use this to
|
// where write operations output a value. Modules use this to
|
||||||
|
|
@ -161,28 +160,16 @@ function EBRPortConfig_Resolved resolvePortCfg(String module_name, String port_n
|
||||||
Bits#(data, data_sz));
|
Bits#(data, data_sz));
|
||||||
let addr_sz = valueOf(addr_sz);
|
let addr_sz = valueOf(addr_sz);
|
||||||
let data_sz = valueOf(data_sz);
|
let data_sz = valueOf(data_sz);
|
||||||
|
let addr_max = case (data_sz) matches
|
||||||
let data_hw_sz = 0;
|
|
||||||
if (data_sz > 18)
|
|
||||||
data_hw_sz = error(sprintf("invalid data width %d for %s port %s, must be 0..18 bits",
|
|
||||||
data_sz, module_name, port_name));
|
|
||||||
else if (data_sz > 9) data_hw_sz = 18;
|
|
||||||
else if (data_sz > 4) data_hw_sz = 9;
|
|
||||||
else if (data_sz > 2) data_hw_sz = 4;
|
|
||||||
else if (data_sz > 1) data_hw_sz = 2;
|
|
||||||
else if (data_sz > 0) data_hw_sz = 1;
|
|
||||||
|
|
||||||
let addr_max = case (data_hw_sz)
|
|
||||||
0: 0;
|
0: 0;
|
||||||
1: 14;
|
1: 14;
|
||||||
2: 13;
|
2: 13;
|
||||||
4: 12;
|
4: 12;
|
||||||
9: 11;
|
9: 11;
|
||||||
18: 10;
|
18: 10;
|
||||||
default: error("unreachable");
|
default: error(sprintf("invalid data width %d for %s port %s, must be one of 0,1,2,4,9,18", data_sz, module_name, port_name));
|
||||||
endcase;
|
endcase;
|
||||||
|
let enabled = data_sz != 0;
|
||||||
let enabled = data_hw_sz != 0;
|
|
||||||
let ret = ?;
|
let ret = ?;
|
||||||
if (enabled)
|
if (enabled)
|
||||||
ret = EBRPortConfig_Resolved{
|
ret = EBRPortConfig_Resolved{
|
||||||
|
|
@ -190,7 +177,7 @@ function EBRPortConfig_Resolved resolvePortCfg(String module_name, String port_n
|
||||||
clk: cfg.clk matches tagged Valid .clk ? clk : defaultClk,
|
clk: cfg.clk matches tagged Valid .clk ? clk : defaultClk,
|
||||||
rstN: cfg.rstN matches tagged Valid .rstN ? rstN : defaultRstN,
|
rstN: cfg.rstN matches tagged Valid .rstN ? rstN : defaultRstN,
|
||||||
addr_width: addr_sz,
|
addr_width: addr_sz,
|
||||||
data_width: data_hw_sz,
|
data_width: data_sz,
|
||||||
register_output: cfg.register_output,
|
register_output: cfg.register_output,
|
||||||
chip_select_addr: cfg.chip_select_addr,
|
chip_select_addr: cfg.chip_select_addr,
|
||||||
write_mode: cfg.write_mode,
|
write_mode: cfg.write_mode,
|
||||||
|
|
@ -482,7 +469,7 @@ module mkEBRCore#(EBRPortConfig cfgA,
|
||||||
endinterface
|
endinterface
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
// mkEBR instantiates one EBR memory block with the given
|
// mkEBRCore instantiates one EBR memory block with the given
|
||||||
// configuration.
|
// configuration.
|
||||||
//
|
//
|
||||||
// This module includes flow control for reads, but unlike the
|
// This module includes flow control for reads, but unlike the
|
||||||
|
|
@ -512,6 +499,55 @@ module mkEBR#(EBRPortConfig cfgA,
|
||||||
DelayLine#(void) latencyA <- mkDelayLine(rcfgA.operation_latency, clocked_by(rcfgA.clk), reset_by(rcfgA.rstN));
|
DelayLine#(void) latencyA <- mkDelayLine(rcfgA.operation_latency, clocked_by(rcfgA.clk), reset_by(rcfgA.rstN));
|
||||||
DelayLine#(void) latencyB <- mkDelayLine(rcfgB.operation_latency, clocked_by(rcfgB.clk), reset_by(rcfgB.rstN));
|
DelayLine#(void) latencyB <- mkDelayLine(rcfgB.operation_latency, clocked_by(rcfgB.clk), reset_by(rcfgB.rstN));
|
||||||
|
|
||||||
|
// WriteOnly#(Bool) portA_start_op = ?;
|
||||||
|
// ReadOnly#(Bool) portA_op_complete = ?;
|
||||||
|
// WriteOnly#(Bool) portB_start_op = ?;
|
||||||
|
// ReadOnly#(Bool) portB_op_complete = ?;
|
||||||
|
|
||||||
|
// // TODO: this variable-depth register chain should be pulled into a
|
||||||
|
// // separate "delay line" module.
|
||||||
|
// if (!rcfgA.enabled) begin
|
||||||
|
// portA_start_op = discardingWriteOnly;
|
||||||
|
// portA_op_complete = constToReadOnly(False);
|
||||||
|
// end
|
||||||
|
// else if (rcfgA.register_output) begin
|
||||||
|
// let syncA1 <- mkDReg(False, clocked_by(rcfgA.clk), reset_by(rcfgA.rstN));
|
||||||
|
// let syncA2 <- mkReg(False, clocked_by(rcfgA.clk), reset_by(rcfgA.rstN));
|
||||||
|
// portA_start_op = regToWriteOnly(syncA1);
|
||||||
|
// portA_op_complete = regToReadOnly(syncA2);
|
||||||
|
|
||||||
|
// (* no_implicit_conditions, fire_when_enabled *)
|
||||||
|
// rule syncA1_to_syncA2;
|
||||||
|
// syncA2 <= syncA1;
|
||||||
|
// endrule
|
||||||
|
// end
|
||||||
|
// else begin
|
||||||
|
// let syncA <- mkDReg(False, clocked_by(rcfgA.clk), reset_by(rcfgA.rstN));
|
||||||
|
// portA_start_op = regToWriteOnly(syncA);
|
||||||
|
// portA_op_complete = regToReadOnly(syncA);
|
||||||
|
// end
|
||||||
|
|
||||||
|
// if (!rcfgB.enabled) begin
|
||||||
|
// portB_start_op = discardingWriteOnly;
|
||||||
|
// portB_op_complete = constToReadOnly(False);
|
||||||
|
// end
|
||||||
|
// else if (rcfgB.register_output) begin
|
||||||
|
// let syncB1 <- mkDReg(False, clocked_by(rcfgB.clk), reset_by(rcfgB.rstN));
|
||||||
|
// let syncB2 <- mkReg(False, clocked_by(rcfgB.clk), reset_by(rcfgB.rstN));
|
||||||
|
// portB_start_op = regToWriteOnly(syncB1);
|
||||||
|
// portB_op_complete = regToReadOnly(syncB2);
|
||||||
|
|
||||||
|
// (* no_implicit_conditions, fire_when_enabled *)
|
||||||
|
// rule syncB1_to_syncB2;
|
||||||
|
// syncB2 <= syncB1;
|
||||||
|
// endrule
|
||||||
|
// end
|
||||||
|
// else begin
|
||||||
|
// let syncB1 <- mkDReg(False, clocked_by(rcfgB.clk), reset_by(rcfgB.rstN));
|
||||||
|
// portB_start_op = regToWriteOnly(syncB1);
|
||||||
|
// portB_op_complete = regToReadOnly(syncB1);
|
||||||
|
// end
|
||||||
|
|
||||||
interface EBRPort portA;
|
interface EBRPort portA;
|
||||||
method Action put(UInt#(3) chip_select, Bool write, addr_a address, data_a datain);
|
method Action put(UInt#(3) chip_select, Bool write, addr_a address, data_a datain);
|
||||||
mem.portA.put(chip_select, write, address, datain);
|
mem.portA.put(chip_select, write, address, datain);
|
||||||
|
|
|
||||||
|
|
@ -18,7 +18,7 @@ module ECP5_RAM(CLKA,
|
||||||
RSTB,
|
RSTB,
|
||||||
DOB);
|
DOB);
|
||||||
|
|
||||||
parameter GSR = "ENABLED";
|
parameter GSR = "AUTO";
|
||||||
parameter RESETMODE = "SYNC";
|
parameter RESETMODE = "SYNC";
|
||||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
parameter ASYNC_RESET_RELEASE = "SYNC";
|
||||||
|
|
||||||
|
|
|
||||||
19
tasks.py
19
tasks.py
|
|
@ -125,25 +125,16 @@ def synth(c, target):
|
||||||
yosys_report = out_yosys / module_name.with_suffix(".stats")
|
yosys_report = out_yosys / module_name.with_suffix(".stats")
|
||||||
yosys_log = out_yosys / module_name.with_suffix(".log")
|
yosys_log = out_yosys / module_name.with_suffix(".log")
|
||||||
yosys_preprocessed = out_yosys / module_name.with_suffix(".v")
|
yosys_preprocessed = out_yosys / module_name.with_suffix(".v")
|
||||||
yosys_preprocessed_rtl = out_yosys / module_name.with_suffix(".rtlil")
|
|
||||||
yosys_preprocessed_graph = out_yosys / module_name.stem
|
|
||||||
yosys_compiled = out_yosys / f"{module_name.stem}_compiled.v"
|
yosys_compiled = out_yosys / f"{module_name.stem}_compiled.v"
|
||||||
with open(yosys_script, "w", encoding="UTF-8") as f:
|
with open(yosys_script, "w", encoding="UTF-8") as f:
|
||||||
f.write(dedent(f"""\
|
f.write(dedent(f"""\
|
||||||
read_verilog -sv -defer {' '.join(str(f) for f in verilog_files)}
|
read_verilog -sv -defer {' '.join(str(f) for f in verilog_files)}
|
||||||
hierarchy -top {module_name}
|
hierarchy -top {module_name}
|
||||||
design -push-copy
|
synth_ecp5 -top {module_name} -run :map_ram
|
||||||
synth_lattice -family ecp5 -abc9 -run :map_ram
|
|
||||||
opt -full
|
|
||||||
clean -purge
|
|
||||||
write_verilog -sv {yosys_preprocessed}
|
write_verilog -sv {yosys_preprocessed}
|
||||||
write_rtlil {yosys_preprocessed_rtl}
|
opt_clean -purge
|
||||||
show -format dot -colors 1 -stretch -viewer none -prefix {yosys_preprocessed_graph}
|
synth_ecp5 -run map_ram: -json {yosys_json}
|
||||||
|
opt_clean -purge
|
||||||
design -pop
|
|
||||||
synth_lattice -family ecp5 -abc9 -no-rw-check
|
|
||||||
clean -purge
|
|
||||||
write_json {yosys_json}
|
|
||||||
write_verilog -sv {yosys_compiled}
|
write_verilog -sv {yosys_compiled}
|
||||||
tee -o {yosys_report} stat
|
tee -o {yosys_report} stat
|
||||||
"""))
|
"""))
|
||||||
|
|
@ -165,7 +156,7 @@ def synth(c, target):
|
||||||
nextpnr_out = out_nextpnr / module_name.with_suffix(".pnr")
|
nextpnr_out = out_nextpnr / module_name.with_suffix(".pnr")
|
||||||
nextpnr_log = out_nextpnr / module_name.with_suffix(".log")
|
nextpnr_log = out_nextpnr / module_name.with_suffix(".log")
|
||||||
nextpnr_timing = out_nextpnr / module_name.with_suffix(".log")
|
nextpnr_timing = out_nextpnr / module_name.with_suffix(".log")
|
||||||
out = c.run(f"nextpnr-ecp5 --85k --detailed-timing-report -l {nextpnr_log} --report {nextpnr_timing} --json {yosys_json} --lpf {pin_map} --package=CABGA381 --speed=6 --textcfg {nextpnr_out}", hide='stderr')
|
out = c.run(f"nextpnr-ecp5 --85k --detailed-timing-report -l {nextpnr_log} --report {nextpnr_timing} --json {yosys_json} --lpf {pin_map} --package=CABGA381 --textcfg {nextpnr_out}") #, hide='stderr')
|
||||||
|
|
||||||
print_filtered_paragraphs(out.stderr, "Device utilisation", "Critical path", "Max frequency", "Max delay", common_prefix="Info: ")
|
print_filtered_paragraphs(out.stderr, "Device utilisation", "Critical path", "Max frequency", "Max delay", common_prefix="Info: ")
|
||||||
print(f" PNR : {nextpnr_out}")
|
print(f" PNR : {nextpnr_out}")
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue