lib/DelayLine_Test.bsv

@@ -9,7 +9,6 @@ import List::*;
 import DelayLine::*;
 
 module mkTB();
-   let testflags <- mkTestFlags();
    let cycles <- mkCycleCounter();
 
    function Stmt testDelayLine(DelayLine#(Int#(8)) delay, Bit#(32) wantDelay);
@@ -17,7 +16,6 @@ module mkTB();
          action
             delay <= 42;
             cycles.reset();
-            if (testflags.verbose)
             $display("  write cycle: %0d", cycles.all);
          endaction
 
@@ -41,7 +39,6 @@ module mkTB();
                   $display("delay line became ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all);
                   $finish;
                end
-               if (testflags.verbose)
                $display("  read cycle: %0d", cycles.all);
             endaction
          endpar
@@ -62,12 +59,10 @@ module mkTB();
                   par
                      action
                         delay0 <= 42;
-                        if (testflags.verbose)
                         $display("  write cycle: %0d", cycles.all);
                      endaction
                      action
                         dynamicAssert(delay0.ready == True, "delay line not ready on same cycle");
-                        if (testflags.verbose)
                         $display("  read cycle: %0d", cycles.all);
                      endaction
                      dynamicAssert(delay0 == 42, "delay line has wrong value");

tasks.py

@@ -213,7 +213,7 @@ def synth(c, target):
     print(f"Wrote bitstream to {bitstream}")
 
 @task
-def test(c, target, verbose=False):
+def test(c, target):
     to_run = []
     for target in expand_test_target(target):
         out_info, out_sim, out_bsc = ensure_build_dirs(target, "info", "sim", "bsc")
@@ -227,8 +227,7 @@ def test(c, target, verbose=False):
         testdata_tgt = testdata_tgt.relative_to(out_sim, walk_up=True)
         testdata.unlink(missing_ok=True)
         testdata.symlink_to(testdata_tgt, target_is_directory=True)
-        cmd = f"./TB -V {target.stem}.vcd {'+v' if verbose else ''}"
-        to_run.append((out_sim, cmd))
+        to_run.append((out_sim, f"./TB -V {target.stem}.vcd"))
     for d, cmd in to_run:
         print("")
         with c.cd(d):

vram/MemArbiter_Test.bsv

@@ -71,7 +71,6 @@ interface TB;
 endinterface
 
 module mkArbiterTB(MemArbiter#(n, Addr) dut, Vector#(m, TestCase#(n)) tests, TB ifc);
-   let testflags <- mkTestFlags();
    let cycles <- mkCycleCounter();
 
    Reg#(Bit#(TLog#(m))) idx <- mkReg(0);
@@ -114,8 +113,7 @@ module mkArbiterTB(MemArbiter#(n, Addr) dut, Vector#(m, TestCase#(n)) tests, TB
          got_grants[i] = dut.ports[i].grant();
 
       $display("RUN %s (%0d)", tests[idx].name, idx);
-      let err = (got_grants != want_grants || got_conflict_out != want_conflict_out);
-      if (err || testflags.verbose) begin
+      if (got_grants != want_grants || got_conflict_out != want_conflict_out) begin
          $display("input:");
          for (Integer i=0; i<valueOf(n); i=i+1)
             $display("    ", $format("%0d", i), ": ", req_s(reqs[i]));
@@ -127,8 +125,8 @@ module mkArbiterTB(MemArbiter#(n, Addr) dut, Vector#(m, TestCase#(n)) tests, TB
 
          $display("  want grants: ", fshow(tests[idx].want_grants));
          $display("  want granted: ", fshow(want_conflict_out));
+         dynamicAssert(False, "wrong arbiter output");
       end
-      dynamicAssert(!err, "wrong arbiter output");
 
       dynamicAssert(cycles == 1, "arbiter took more than 0 cycles");