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base: dave:719339e69f91246298e6b4310efc17cacbf11c88
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compare: dave:4b6b34e131363d8eca9bb0114b76db9f2350236c
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dave:main

No commits in common. "719339e69f91246298e6b4310efc17cacbf11c88" and "4b6b34e131363d8eca9bb0114b76db9f2350236c" have entirely different histories.
719339e69f ... 4b6b34e131

3 changed files with 14 additions and 22 deletions
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5
lib/DelayLine_Test.bsv
View File

@ -9,7 +9,6 @@ import List::*;
import DelayLine::*; import DelayLine::*;
module mkTB(); module mkTB();
let testflags <- mkTestFlags();
let cycles <- mkCycleCounter(); let cycles <- mkCycleCounter();
function Stmt testDelayLine(DelayLine#(Int#(8)) delay, Bit#(32) wantDelay); function Stmt testDelayLine(DelayLine#(Int#(8)) delay, Bit#(32) wantDelay);
@ -17,7 +16,6 @@ module mkTB();
action action
delay <= 42; delay <= 42;
cycles.reset(); cycles.reset();
if (testflags.verbose)
$display(" write cycle: %0d", cycles.all); $display(" write cycle: %0d", cycles.all);
endaction endaction
@ -41,7 +39,6 @@ module mkTB();
$display("delay line became ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all); $display("delay line became ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all);
$finish; $finish;
end end
if (testflags.verbose)
$display(" read cycle: %0d", cycles.all); $display(" read cycle: %0d", cycles.all);
endaction endaction
endpar endpar
@ -62,12 +59,10 @@ module mkTB();
par par
action action
delay0 <= 42; delay0 <= 42;
if (testflags.verbose)
$display(" write cycle: %0d", cycles.all); $display(" write cycle: %0d", cycles.all);
endaction endaction
action action
dynamicAssert(delay0.ready == True, "delay line not ready on same cycle"); dynamicAssert(delay0.ready == True, "delay line not ready on same cycle");
if (testflags.verbose)
$display(" read cycle: %0d", cycles.all); $display(" read cycle: %0d", cycles.all);
endaction endaction
dynamicAssert(delay0 == 42, "delay line has wrong value"); dynamicAssert(delay0 == 42, "delay line has wrong value");

5
tasks.py
View File

@ -213,7 +213,7 @@ def synth(c, target):
print(f"Wrote bitstream to {bitstream}") print(f"Wrote bitstream to {bitstream}")
@task @task
def test(c, target, verbose=False): def test(c, target):
to_run = [] to_run = []
for target in expand_test_target(target): for target in expand_test_target(target):
out_info, out_sim, out_bsc = ensure_build_dirs(target, "info", "sim", "bsc") out_info, out_sim, out_bsc = ensure_build_dirs(target, "info", "sim", "bsc")
@ -227,8 +227,7 @@ def test(c, target, verbose=False):
testdata_tgt = testdata_tgt.relative_to(out_sim, walk_up=True) testdata_tgt = testdata_tgt.relative_to(out_sim, walk_up=True)
testdata.unlink(missing_ok=True) testdata.unlink(missing_ok=True)
testdata.symlink_to(testdata_tgt, target_is_directory=True) testdata.symlink_to(testdata_tgt, target_is_directory=True)
cmd = f"./TB -V {target.stem}.vcd {'+v' if verbose else ''}" to_run.append((out_sim, f"./TB -V {target.stem}.vcd"))
to_run.append((out_sim, cmd))
for d, cmd in to_run: for d, cmd in to_run:
print("") print("")
with c.cd(d): with c.cd(d):

6
vram/MemArbiter_Test.bsv
View File

@ -71,7 +71,6 @@ interface TB;
endinterface endinterface
module mkArbiterTB(MemArbiter#(n, Addr) dut, Vector#(m, TestCase#(n)) tests, TB ifc); module mkArbiterTB(MemArbiter#(n, Addr) dut, Vector#(m, TestCase#(n)) tests, TB ifc);
let testflags <- mkTestFlags();
let cycles <- mkCycleCounter(); let cycles <- mkCycleCounter();
Reg#(Bit#(TLog#(m))) idx <- mkReg(0); Reg#(Bit#(TLog#(m))) idx <- mkReg(0);
@ -114,8 +113,7 @@ module mkArbiterTB(MemArbiter#(n, Addr) dut, Vector#(m, TestCase#(n)) tests, TB
got_grants[i] = dut.ports[i].grant(); got_grants[i] = dut.ports[i].grant();
$display("RUN %s (%0d)", tests[idx].name, idx); $display("RUN %s (%0d)", tests[idx].name, idx);
let err = (got_grants != want_grants || got_conflict_out != want_conflict_out); if (got_grants != want_grants || got_conflict_out != want_conflict_out) begin
if (err || testflags.verbose) begin
$display("input:"); $display("input:");
for (Integer i=0; i<valueOf(n); i=i+1) for (Integer i=0; i<valueOf(n); i=i+1)
$display(" ", $format("%0d", i), ": ", req_s(reqs[i])); $display(" ", $format("%0d", i), ": ", req_s(reqs[i]));
@ -127,8 +125,8 @@ module mkArbiterTB(MemArbiter#(n, Addr) dut, Vector#(m, TestCase#(n)) tests, TB
$display(" want grants: ", fshow(tests[idx].want_grants)); $display(" want grants: ", fshow(tests[idx].want_grants));
$display(" want granted: ", fshow(want_conflict_out)); $display(" want granted: ", fshow(want_conflict_out));
dynamicAssert(False, "wrong arbiter output");
end end
dynamicAssert(!err, "wrong arbiter output");
dynamicAssert(cycles == 1, "arbiter took more than 0 cycles"); dynamicAssert(cycles == 1, "arbiter took more than 0 cycles");