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2 changed files with 5 additions and 1 deletions

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@ -77,6 +77,11 @@ module mkDelayLine(Integer delay_cycles, DelayLine#(a) ifc)
delay = cons(r, delay);
end
// pump_line ingests a new value into the first register in the
// line, and shifts older values one register down. The
// registers always shift forward even when nobody's writing, in
// which case that slot in the pipeline is occupied by an empty
// Maybe.
(* no_implicit_conditions, fire_when_enabled *)
rule pump_line;
delay[0] <= inputVal.wget();

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@ -180,7 +180,6 @@ def test(c, target):
testdata_tgt = testdata_tgt.relative_to(out_sim, walk_up=True)
testdata.unlink(missing_ok=True)
testdata.symlink_to(testdata_tgt, target_is_directory=True)
print("before run")
with c.cd(out_sim):
c.run(f"./TB -V {target.stem}.vcd")