Compare commits

..

3 Commits

3 changed files with 22 additions and 14 deletions

View File

@ -9,6 +9,7 @@ import List::*;
import DelayLine::*; import DelayLine::*;
module mkTB(); module mkTB();
let testflags <- mkTestFlags();
let cycles <- mkCycleCounter(); let cycles <- mkCycleCounter();
function Stmt testDelayLine(DelayLine#(Int#(8)) delay, Bit#(32) wantDelay); function Stmt testDelayLine(DelayLine#(Int#(8)) delay, Bit#(32) wantDelay);
@ -16,16 +17,17 @@ module mkTB();
action action
delay <= 42; delay <= 42;
cycles.reset(); cycles.reset();
$display(" write cycle: %0d", cycles.all); if (testflags.verbose)
$display(" write cycle: %0d", cycles.all);
endaction endaction
repeat (wantDelay-1) repeat (wantDelay-1)
action action
if (delay.ready) begin if (delay.ready) begin
$display("delay line ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all); $display("delay line ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all);
$finish; $finish;
end end
endaction endaction
// Check the value coming off the delay line and the timing // Check the value coming off the delay line and the timing
// separately, since the delay line read can be blocked by // separately, since the delay line read can be blocked by
@ -39,7 +41,8 @@ module mkTB();
$display("delay line became ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all); $display("delay line became ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all);
$finish; $finish;
end end
$display(" read cycle: %0d", cycles.all); if (testflags.verbose)
$display(" read cycle: %0d", cycles.all);
endaction endaction
endpar endpar
@ -59,11 +62,13 @@ module mkTB();
par par
action action
delay0 <= 42; delay0 <= 42;
$display(" write cycle: %0d", cycles.all); if (testflags.verbose)
$display(" write cycle: %0d", cycles.all);
endaction endaction
action action
dynamicAssert(delay0.ready == True, "delay line not ready on same cycle"); dynamicAssert(delay0.ready == True, "delay line not ready on same cycle");
$display(" read cycle: %0d", cycles.all); if (testflags.verbose)
$display(" read cycle: %0d", cycles.all);
endaction endaction
dynamicAssert(delay0 == 42, "delay line has wrong value"); dynamicAssert(delay0 == 42, "delay line has wrong value");
endpar endpar

View File

@ -213,7 +213,7 @@ def synth(c, target):
print(f"Wrote bitstream to {bitstream}") print(f"Wrote bitstream to {bitstream}")
@task @task
def test(c, target): def test(c, target, verbose=False):
to_run = [] to_run = []
for target in expand_test_target(target): for target in expand_test_target(target):
out_info, out_sim, out_bsc = ensure_build_dirs(target, "info", "sim", "bsc") out_info, out_sim, out_bsc = ensure_build_dirs(target, "info", "sim", "bsc")
@ -227,7 +227,8 @@ def test(c, target):
testdata_tgt = testdata_tgt.relative_to(out_sim, walk_up=True) testdata_tgt = testdata_tgt.relative_to(out_sim, walk_up=True)
testdata.unlink(missing_ok=True) testdata.unlink(missing_ok=True)
testdata.symlink_to(testdata_tgt, target_is_directory=True) testdata.symlink_to(testdata_tgt, target_is_directory=True)
to_run.append((out_sim, f"./TB -V {target.stem}.vcd")) cmd = f"./TB -V {target.stem}.vcd {'+v' if verbose else ''}"
to_run.append((out_sim, cmd))
for d, cmd in to_run: for d, cmd in to_run:
print("") print("")
with c.cd(d): with c.cd(d):

View File

@ -71,6 +71,7 @@ interface TB;
endinterface endinterface
module mkArbiterTB(MemArbiter#(n, Addr) dut, Vector#(m, TestCase#(n)) tests, TB ifc); module mkArbiterTB(MemArbiter#(n, Addr) dut, Vector#(m, TestCase#(n)) tests, TB ifc);
let testflags <- mkTestFlags();
let cycles <- mkCycleCounter(); let cycles <- mkCycleCounter();
Reg#(Bit#(TLog#(m))) idx <- mkReg(0); Reg#(Bit#(TLog#(m))) idx <- mkReg(0);
@ -113,7 +114,8 @@ module mkArbiterTB(MemArbiter#(n, Addr) dut, Vector#(m, TestCase#(n)) tests, TB
got_grants[i] = dut.ports[i].grant(); got_grants[i] = dut.ports[i].grant();
$display("RUN %s (%0d)", tests[idx].name, idx); $display("RUN %s (%0d)", tests[idx].name, idx);
if (got_grants != want_grants || got_conflict_out != want_conflict_out) begin let err = (got_grants != want_grants || got_conflict_out != want_conflict_out);
if (err || testflags.verbose) begin
$display("input:"); $display("input:");
for (Integer i=0; i<valueOf(n); i=i+1) for (Integer i=0; i<valueOf(n); i=i+1)
$display(" ", $format("%0d", i), ": ", req_s(reqs[i])); $display(" ", $format("%0d", i), ": ", req_s(reqs[i]));
@ -125,8 +127,8 @@ module mkArbiterTB(MemArbiter#(n, Addr) dut, Vector#(m, TestCase#(n)) tests, TB
$display(" want grants: ", fshow(tests[idx].want_grants)); $display(" want grants: ", fshow(tests[idx].want_grants));
$display(" want granted: ", fshow(want_conflict_out)); $display(" want granted: ", fshow(want_conflict_out));
dynamicAssert(False, "wrong arbiter output");
end end
dynamicAssert(!err, "wrong arbiter output");
dynamicAssert(cycles == 1, "arbiter took more than 0 cycles"); dynamicAssert(cycles == 1, "arbiter took more than 0 cycles");