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3 Commits
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719339e69f
Author | SHA1 | Date |
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David Anderson | 719339e69f | |
David Anderson | 80391cefee | |
David Anderson | 1ca4ccff99 |
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@ -9,6 +9,7 @@ import List::*;
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import DelayLine::*;
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import DelayLine::*;
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module mkTB();
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module mkTB();
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let testflags <- mkTestFlags();
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let cycles <- mkCycleCounter();
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let cycles <- mkCycleCounter();
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function Stmt testDelayLine(DelayLine#(Int#(8)) delay, Bit#(32) wantDelay);
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function Stmt testDelayLine(DelayLine#(Int#(8)) delay, Bit#(32) wantDelay);
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@ -16,6 +17,7 @@ module mkTB();
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action
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action
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delay <= 42;
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delay <= 42;
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cycles.reset();
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cycles.reset();
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if (testflags.verbose)
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$display(" write cycle: %0d", cycles.all);
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$display(" write cycle: %0d", cycles.all);
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endaction
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endaction
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@ -39,6 +41,7 @@ module mkTB();
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$display("delay line became ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all);
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$display("delay line became ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all);
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$finish;
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$finish;
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end
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end
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if (testflags.verbose)
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$display(" read cycle: %0d", cycles.all);
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$display(" read cycle: %0d", cycles.all);
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endaction
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endaction
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endpar
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endpar
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@ -59,10 +62,12 @@ module mkTB();
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par
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par
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action
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action
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delay0 <= 42;
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delay0 <= 42;
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if (testflags.verbose)
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$display(" write cycle: %0d", cycles.all);
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$display(" write cycle: %0d", cycles.all);
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endaction
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endaction
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action
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action
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dynamicAssert(delay0.ready == True, "delay line not ready on same cycle");
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dynamicAssert(delay0.ready == True, "delay line not ready on same cycle");
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if (testflags.verbose)
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$display(" read cycle: %0d", cycles.all);
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$display(" read cycle: %0d", cycles.all);
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endaction
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endaction
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dynamicAssert(delay0 == 42, "delay line has wrong value");
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dynamicAssert(delay0 == 42, "delay line has wrong value");
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5
tasks.py
5
tasks.py
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@ -213,7 +213,7 @@ def synth(c, target):
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print(f"Wrote bitstream to {bitstream}")
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print(f"Wrote bitstream to {bitstream}")
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@task
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@task
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def test(c, target):
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def test(c, target, verbose=False):
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to_run = []
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to_run = []
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for target in expand_test_target(target):
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for target in expand_test_target(target):
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out_info, out_sim, out_bsc = ensure_build_dirs(target, "info", "sim", "bsc")
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out_info, out_sim, out_bsc = ensure_build_dirs(target, "info", "sim", "bsc")
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@ -227,7 +227,8 @@ def test(c, target):
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testdata_tgt = testdata_tgt.relative_to(out_sim, walk_up=True)
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testdata_tgt = testdata_tgt.relative_to(out_sim, walk_up=True)
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testdata.unlink(missing_ok=True)
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testdata.unlink(missing_ok=True)
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testdata.symlink_to(testdata_tgt, target_is_directory=True)
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testdata.symlink_to(testdata_tgt, target_is_directory=True)
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to_run.append((out_sim, f"./TB -V {target.stem}.vcd"))
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cmd = f"./TB -V {target.stem}.vcd {'+v' if verbose else ''}"
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to_run.append((out_sim, cmd))
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for d, cmd in to_run:
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for d, cmd in to_run:
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print("")
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print("")
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with c.cd(d):
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with c.cd(d):
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@ -71,6 +71,7 @@ interface TB;
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endinterface
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endinterface
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module mkArbiterTB(MemArbiter#(n, Addr) dut, Vector#(m, TestCase#(n)) tests, TB ifc);
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module mkArbiterTB(MemArbiter#(n, Addr) dut, Vector#(m, TestCase#(n)) tests, TB ifc);
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let testflags <- mkTestFlags();
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let cycles <- mkCycleCounter();
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let cycles <- mkCycleCounter();
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Reg#(Bit#(TLog#(m))) idx <- mkReg(0);
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Reg#(Bit#(TLog#(m))) idx <- mkReg(0);
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@ -113,7 +114,8 @@ module mkArbiterTB(MemArbiter#(n, Addr) dut, Vector#(m, TestCase#(n)) tests, TB
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got_grants[i] = dut.ports[i].grant();
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got_grants[i] = dut.ports[i].grant();
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$display("RUN %s (%0d)", tests[idx].name, idx);
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$display("RUN %s (%0d)", tests[idx].name, idx);
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if (got_grants != want_grants || got_conflict_out != want_conflict_out) begin
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let err = (got_grants != want_grants || got_conflict_out != want_conflict_out);
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if (err || testflags.verbose) begin
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$display("input:");
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$display("input:");
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for (Integer i=0; i<valueOf(n); i=i+1)
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for (Integer i=0; i<valueOf(n); i=i+1)
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$display(" ", $format("%0d", i), ": ", req_s(reqs[i]));
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$display(" ", $format("%0d", i), ": ", req_s(reqs[i]));
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@ -125,8 +127,8 @@ module mkArbiterTB(MemArbiter#(n, Addr) dut, Vector#(m, TestCase#(n)) tests, TB
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$display(" want grants: ", fshow(tests[idx].want_grants));
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$display(" want grants: ", fshow(tests[idx].want_grants));
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$display(" want granted: ", fshow(want_conflict_out));
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$display(" want granted: ", fshow(want_conflict_out));
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dynamicAssert(False, "wrong arbiter output");
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end
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end
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dynamicAssert(!err, "wrong arbiter output");
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dynamicAssert(cycles == 1, "arbiter took more than 0 cycles");
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dynamicAssert(cycles == 1, "arbiter took more than 0 cycles");
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