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f1e705fd31
Author | SHA1 | Date |
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David Anderson | f1e705fd31 | |
David Anderson | 85e27554ec |
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package DelayLine;
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import List::*;
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// A DelayLine mirrors writes back as reads after a number of delay
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// cycles. Delay lines are pipelined and multiple values can be "in
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// flight" at once.
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//
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// Reads block until a value is available, but the DelayLine doesn't
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// stall if there are no readers - the value is available for reading
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// after the set delay, and is lost if not read by anything.
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//
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// For callers that need to check for a value without tripping over an
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// implicit condition, ready() can poll the delay line's output
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// without blocking.
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interface DelayLine#(type value);
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method Action _write (value v);
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method value _read();
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(* always_ready *)
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method Bool ready();
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endinterface
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// mkDelayLine constructs a DelayLine with delay_cycles of latency
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// between writes and reads. delay_cycles may be zero, with the result
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// being Wire/RWire like scheduling semantics.
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module mkDelayLine(Integer delay_cycles, DelayLine#(a) ifc)
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provisos (Bits#(a, a_sz));
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// In most cases a DelayLine is a pipeline of registers through
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// which values flow, and so it inherits the scheduling properties
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// of registers: all reads from the delay line happen before any
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// writes take effect.
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//
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// The exception is when the caller asks for zero cycles of delay:
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// in that case, a write must be visible to reads within the same
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// cycle, and thus the write to the delay line must execute before
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// any reads.
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//
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// So, handle a delay of 0 cycles specially and implement it as an
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// RWire, which has write-before-read behavior. Otherwise, build a
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// pipeline of registers with read-before-write behavior.
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//
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// You might wonder why even bother allowing a DelayLine with zero
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// delay. It's because doing so is handy in parameterized
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// modules. Say for example you're wrapping a blackbox module that
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// has optional input and output registers. Depending on the
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// parameters, the in->out delay could be 0 cycles (pure
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// combinatorial circuit), 1 cycle (input or output register) or 2
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// cycles (input and output register). It's very handy to be able
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// to plop down a DelayLine regardless of the requested
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// configuration, and have it gracefully go all the way to zero
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// latency.
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if (delay_cycles == 0) begin
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RWire#(a) w <- mkRWire();
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method Action _write(a value);
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w.wset(value);
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endmethod
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method a _read() if (w.wget matches tagged Valid .val);
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return val;
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endmethod
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method Bool ready();
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return isValid(w.wget);
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endmethod
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end
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else begin
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RWire#(a) inputVal <- mkRWire;
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// Note that in rules and modules, for loops get unrolled
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// statically at compile time. We're not specifying a circuit
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// that runs a loop in hardware here, this is shorthand for
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// "splat out N registers and wire them together in a line".
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List#(Reg#(Maybe#(a))) delay = Nil;
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for (Integer i = 0; i < delay_cycles; i = i+1) begin
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let r <- mkReg(Invalid);
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delay = cons(r, delay);
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end
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(* no_implicit_conditions, fire_when_enabled *)
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rule pump_line;
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delay[0] <= inputVal.wget();
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for (Integer i = 0; i < delay_cycles-1; i = i+1)
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delay[i+1] <= delay[i];
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endrule
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method Action _write(a value);
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inputVal.wset(value);
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endmethod
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method a _read() if (delay[delay_cycles-1] matches tagged Valid .val);
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return val;
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endmethod
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method Bool ready();
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return isValid(delay[delay_cycles-1]);
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endmethod
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end
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endmodule
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endpackage
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@ -0,0 +1,85 @@
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package DelayLine_Test;
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import Assert::*;
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import StmtFSM::*;
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import Testing::*;
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import Printf::*;
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import List::*;
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import DelayLine::*;
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module mkTB();
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let cycles <- mkCycleCounter();
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function Stmt testDelayLine(DelayLine#(Int#(8)) delay, Bit#(32) wantDelay);
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seq
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action
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delay <= 42;
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cycles.reset();
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$display(" write cycle: %0d", cycles.all);
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endaction
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repeat (wantDelay-1)
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action
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if (delay.ready) begin
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$display("delay line ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all);
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$finish;
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end
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endaction
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// Check the value coming off the delay line and the timing
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// separately, since the delay line read can be blocked by
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// implicit conditions.
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par
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dynamicAssert(delay == 42, "delay output was wrong value");
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action
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dynamicAssert(delay.ready == True, "delay line not ready when expected");
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if (cycles != wantDelay) begin
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$display("delay line became ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all);
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$finish;
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end
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$display(" read cycle: %0d", cycles.all);
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endaction
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endpar
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dynamicAssert(delay.ready == False, "delay line still ready after value yield");
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endseq;
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endfunction
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let delay0 <- mkDelayLine(0);
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let delay1 <- mkDelayLine(1);
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let delay2 <- mkDelayLine(2);
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let delay3 <- mkDelayLine(3);
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let delay4 <- mkDelayLine(4);
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let test0 = seq
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dynamicAssert(delay0.ready == False, "delay line ready before put");
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par
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action
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delay0 <= 42;
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$display(" write cycle: %0d", cycles.all);
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endaction
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action
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dynamicAssert(delay0.ready == True, "delay line not ready on same cycle");
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$display(" read cycle: %0d", cycles.all);
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endaction
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dynamicAssert(delay0 == 42, "delay line has wrong value");
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endpar
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dynamicAssert(delay0.ready == False, "delay line ready without write");
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endseq;
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runTest(100,
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mkTest("DelayLine", seq
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mkTest("DelayLine/0", test0);
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mkTest("DelayLine/1", testDelayLine(delay1, 1));
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mkTest("DelayLine/2", testDelayLine(delay2, 2));
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mkTest("DelayLine/3", testDelayLine(delay3, 3));
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mkTest("DelayLine/4", testDelayLine(delay4, 4));
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endseq));
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endmodule
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endpackage
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@ -2,21 +2,64 @@ package Testing;
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import Assert::*;
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import StmtFSM::*;
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import Cntrs::*;
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module mkTestCycleLimit#(Integer max_cycles)();
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Reg#(UInt#(64)) c <- mkReg(fromInteger(max_cycles));
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// A CycleCounter keeps a count of total elapsed cycles in a
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// simulation, as well as cycles since the last reset.
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interface CycleCounter;
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// _read returns the number of cycles since the last time reset()
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// was called.
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method Bit#(32) _read();
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// reset resets the cycle counter. The counter will read 1 on the
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// cycle following the call to reset.
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method Action reset();
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rule count;
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dynamicAssert(c > 0, "FAIL: test timed out");
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c <= c-1;
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// all returns the number of cycles elapsed since simulation start,
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// for use in $display and the like.
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method Bit#(32) all();
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endinterface
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module mkCycleCounter(CycleCounter);
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let total <- mkCount(0);
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let cnt <- mkCount(0);
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(* no_implicit_conditions, fire_when_enabled *)
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rule count_up;
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cnt.incr(1);
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total.incr(1);
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endrule
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method _read = cnt._read;
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method Action reset();
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cnt.update(0);
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endmethod
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method all = total._read;
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endmodule
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module mkTest#(String name, RStmt#(Bit#(0)) test)();
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mkAutoFSM(seq
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$display("RUN ", name);
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// mkTest runs the given test, printing status text before and after
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// the run. Tests can be nested.
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function Stmt mkTest(String name, Stmt test);
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seq
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$display("RUN %s", name);
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test;
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$display("OK %s", name);
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endseq;
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endfunction
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// runTest runs the given test with a timeout.
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module runTest(Integer cycle_limit, Stmt test, Empty ifc);
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Bit#(32) max = fromInteger(cycle_limit);
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let cnt <- mkCount(0);
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(* no_implicit_conditions, fire_when_enabled *)
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rule cycle_deadline;
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dynamicAssert(cnt < max, "Test timed out");
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cnt.incr(1);
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endrule
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mkAutoFSM(seq
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$display("Running test with %0d cycle timeout", max);
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test;
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$display("OK ", name);
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endseq);
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endmodule
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12
tasks.py
12
tasks.py
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@ -92,10 +92,15 @@ def build(c, target="."):
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c.run(f"bsc -aggressive-conditions -check-assert -u -verilog -info-dir {out_info} -vdir {out_verilog} -bdir {out_bsc} -p {target.parent}:lib:%/Libraries -show-module-use -show-compiles {target}")
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module_name = Path(f"mk{target.stem}")
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verilog_files.append(out_verilog / module_name.with_suffix(".v"))
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verilog_main_file = out_verilog / module_name.with_suffix(".v")
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if verilog_main_file.is_file():
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verilog_files.append(verilog_main_file)
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use_file = out_verilog / module_name.with_suffix(".use")
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if use_file.is_file():
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with open(out_verilog / module_name.with_suffix(".use")) as f:
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verilog_files.extend(find_verilog_modules(c, f.read().splitlines()))
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if verilog_files:
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print("\nVerilog files for synthesis:")
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for v in verilog_files:
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print(" "+str(v))
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@ -110,6 +115,9 @@ def synth(c, target):
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module_name = Path(f"mk{target.stem}")
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verilog_files = build(c, target)
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if not verilog_files:
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print("\nWARNING: bluespec compile didn't output any verilog files, did you (* synthesize *) something?")
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return
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phase("Logic synthesis")
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yosys_script = out_yosys / "script.ys"
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print(f"Wrote bitstream to {bitstream}")
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@task
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def test(c, target="."):
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def test(c, target):
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for target in expand_test_target(target):
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out_info, out_sim, out_bsc = ensure_build_dirs(target, "info", "sim", "bsc")
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c.run(f"bsc -show-schedule -aggressive-conditions -check-assert -u -sim -info-dir {out_info} -simdir {out_sim} -bdir {out_bsc} -g mkTB -p {target.parent}:lib:%/Libraries {target}")
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