Add some early testing harness for the sim DP16KD

tasks.py: print one more intermediate output path
sim/tb: add "bad" signals to make it easier to see wrong outputs
2024-08-30 22:14:10 -07:00 · 2024-08-30 20:06:36 -07:00 · 2024-08-30 20:00:11 -07:00 · 2024-08-30 19:56:08 -07:00
7 changed files with 347 additions and 137 deletions
--- a/sim/.gtkwaverc
+++ b/sim/.gtkwaverc
@ -0,0 +1 @@
+splash_disable on
--- a/sim/DP16KD.v
+++ b/sim/DP16KD.v
@ -29,39 +29,45 @@ module DP16KD__INTERNAL#(

  wire [DATA_WIDTH-1:0] undef = {DATA_WIDTH{1'bx}};

-  if (RESETMODE == "SYNC") begin : sync_ram
-    always @(posedge CLKA) begin
-      if (RSTA)
-        DOA <= {DATA_WIDTH {1'b0}};
-      else if (CEA) begin
-        if (WEA) begin
-          ram[ADA] <= DIA;
-          case (WRITEMODE_A)
-            "NORMAL": DOA <= undef;
-            "WRITETHROUGH": DOA <= DIA;
-            "READBEFOREWRITE": DOA <= ram[ADA];
-          endcase
-        end
-        else
-          DOA <= ram[ADA];
-      end
-    end
+  wire addr_collision = ADA == ADB;
+  wire write_collision = addr_collision && WEA && WEB;
+  wire read_collision = addr_collision && (WEA || WEB);

-    always @(posedge CLKB) begin
-      if (RSTB)
-        DOB <= {DATA_WIDTH {1'b0}};
-      else if (CEB) begin
-        if (WEB) begin
-          ram[ADB] <= DIB;
-          case (WRITEMODE_B)
-            "NORMAL": DOB <= undef;
-            "WRITETHROUGH": DOB <= DIB;
-            "READBEFOREWRITE": DOB <= ram[ADB];
-          endcase
+  if (RESETMODE == "SYNC") begin : sync_ram
+    always @(posedge CLKA, posedge CLKB) begin
+      if (CLKA) begin
+        if (RSTA)
+          DOA <= {DATA_WIDTH {1'b0}};
+        else if (CEA) begin
+          if (WEA) begin
+            ram[ADA] <= write_collision ? undef : DIA;
+            case (WRITEMODE_A)
+              "NORMAL": DOA <= undef;
+              "WRITETHROUGH": DOA <= DIA;
+              "READBEFOREWRITE": DOA <= read_collision ? undef : ram[ADA];
+            endcase
+          end
+          else
+            DOA <= read_collision ? undef : ram[ADA];
        end
-        else
-          DOB <= ram[ADB];
-      end
+      end // if (CLKA)
+
+      if (CLKB) begin
+        if (RSTB)
+          DOB <= {DATA_WIDTH {1'b0}};
+        else if (CEB) begin
+          if (WEB) begin
+            ram[ADB] <= write_collision ? undef : DIB;
+            case (WRITEMODE_B)
+              "NORMAL": DOB <= undef;
+              "WRITETHROUGH": DOB <= DIB;
+              "READBEFOREWRITE": DOB <= read_collision ? undef : ram[ADB];
+            endcase
+          end
+          else
+            DOB <= read_collision ? undef : ram[ADB];
+        end
+      end // if (CLKB)
    end
  end // if (RESETMODE == "SYNC")
  else begin : async_ram
--- a/sim/run.sh
+++ b/sim/run.sh
@ -0,0 +1,38 @@
+#!/usr/bin/env bash
+
+set -euo pipefail
+
+run() {
+    base="$1"
+    variant="$2"
+    shift 2
+
+    mkdir -p gen
+    iverilog -Wall -o test.out "$@" "tb/tb_DP16KD_${base}.v" DP16KD.v
+    ./test.out
+    rm -f test.out
+    dir=$(readlink -f `dirname $0`)
+    vcdfile="${variant}.vcd"
+    mv tb.vcd "${dir}/gen/$vcdfile"
+    gtkwfile="${variant}.gtkw"
+    cp tb_cfg.gtkw "${dir}/gen/$gtkwfile"
+    perl -p -e "s#WORKING_DIR#$dir#g;" -e "s#VCDFILE#${vcdfile}#g;" -e "s#GTKWFILE#${gtkwfile}#g;" <tb_cfg.gtkw >"${dir}/gen/$gtkwfile"
+}
+
+rm -rf gen
+
+run sync_same_width 18b_sync_same_width \
+    -P tb.DATA_WIDTH_A=18 -P tb.DATA_WIDTH_B=18 \
+    -P tb.ADDR_WIDTH_A=10 -P tb.ADDR_WIDTH_B=10
+run sync_same_width 9b_sync_same_width \
+    -P tb.DATA_WIDTH_A=9 -P tb.DATA_WIDTH_B=9 \
+    -P tb.ADDR_WIDTH_A=11 -P tb.ADDR_WIDTH_B=11
+run sync_same_width 4b_sync_same_width \
+    -P tb.DATA_WIDTH_A=4 -P tb.DATA_WIDTH_B=4 \
+    -P tb.ADDR_WIDTH_A=12 -P tb.ADDR_WIDTH_B=12
+run sync_same_width 2b_sync_same_width \
+    -P tb.DATA_WIDTH_A=2 -P tb.DATA_WIDTH_B=2 \
+    -P tb.ADDR_WIDTH_A=13 -P tb.ADDR_WIDTH_B=13
+run sync_same_width 1b_sync_same_width \
+    -P tb.DATA_WIDTH_A=1 -P tb.DATA_WIDTH_B=1 \
+    -P tb.ADDR_WIDTH_A=14 -P tb.ADDR_WIDTH_B=14
--- a/sim/tb/tb_DP16KD_18b_sync_nowriteout_unregistered.v
+++ b/sim/tb/tb_DP16KD_18b_sync_nowriteout_unregistered.v
@ -1,106 +0,0 @@
-module tb_DP16KD_18b_sync_nowriteout_unregistered();
-  reg CLKA=0, RSTA=0, CEA=0, OCEA=0, WEA=0;
-  reg CLKB=0, RSTB=0, CEB=0, OCEB=0, WEB=0;
-  reg [2:0] CSA=0, CSB=0;
-  reg [13:0] ADA, ADB;
-  reg [17:0] DIA, DIB;
-  wire [17:0] DOA, DOB;
-  reg [239:0] TESTNAME;
-
-  DP16KD ram(.CLKA(CLKA), .RSTA(RSTA), .CEA(CEA), .OCEA(OCEA), .WEA(WEA),
-             .CSA2(CSA[2]), .CSA1(CSA[1]), .CSA0(CSA[0]),
-             .ADA13(ADA[13]), .ADA12(ADA[12]), .ADA11(ADA[11]), .ADA10(ADA[10]), .ADA9(ADA[9]), .ADA8(ADA[8]), .ADA7(ADA[7]), .ADA6(ADA[6]), .ADA5(ADA[5]), .ADA4(ADA[4]), .ADA3(ADA[3]), .ADA2(ADA[2]), .ADA1(ADA[1]), .ADA0(ADA[0]),
-             .DIA17(DIA[17]), .DIA16(DIA[16]), .DIA15(DIA[15]), .DIA14(DIA[14]), .DIA13(DIA[13]), .DIA12(DIA[12]), .DIA11(DIA[11]), .DIA10(DIA[10]), .DIA9(DIA[9]), .DIA8(DIA[8]), .DIA7(DIA[7]), .DIA6(DIA[6]), .DIA5(DIA[5]), .DIA4(DIA[4]), .DIA3(DIA[3]), .DIA2(DIA[2]), .DIA1(DIA[1]), .DIA0(DIA[0]),
-             .DOA17(DOA[17]), .DOA16(DOA[16]), .DOA15(DOA[15]), .DOA14(DOA[14]), .DOA13(DOA[13]), .DOA12(DOA[12]), .DOA11(DOA[11]), .DOA10(DOA[10]), .DOA9(DOA[9]), .DOA8(DOA[8]), .DOA7(DOA[7]), .DOA6(DOA[6]), .DOA5(DOA[5]), .DOA4(DOA[4]), .DOA3(DOA[3]), .DOA2(DOA[2]), .DOA1(DOA[1]), .DOA0(DOA[0]),
-
-             .CLKB(CLKB), .RSTB(RSTB), .CEB(CEB), .OCEB(OCEB), .WEB(WEB),
-             .CSB2(CSB[2]), .CSB1(CSB[1]), .CSB0(CSB[0]),
-             .ADB13(ADB[13]), .ADB12(ADB[12]), .ADB11(ADB[11]), .ADB10(ADB[10]), .ADB9(ADB[9]), .ADB8(ADB[8]), .ADB7(ADB[7]), .ADB6(ADB[6]), .ADB5(ADB[5]), .ADB4(ADB[4]), .ADB3(ADB[3]), .ADB2(ADB[2]), .ADB1(ADB[1]), .ADB0(ADB[0]),
-             .DIB17(DIB[17]), .DIB16(DIB[16]), .DIB15(DIB[15]), .DIB14(DIB[14]), .DIB13(DIB[13]), .DIB12(DIB[12]), .DIB11(DIB[11]), .DIB10(DIB[10]), .DIB9(DIB[9]), .DIB8(DIB[8]), .DIB7(DIB[7]), .DIB6(DIB[6]), .DIB5(DIB[5]), .DIB4(DIB[4]), .DIB3(DIB[3]), .DIB2(DIB[2]), .DIB1(DIB[1]), .DIB0(DIB[0]),
-             .DOB17(DOB[17]), .DOB16(DOB[16]), .DOB15(DOB[15]), .DOB14(DOB[14]), .DOB13(DOB[13]), .DOB12(DOB[12]), .DOB11(DOB[11]), .DOB10(DOB[10]), .DOB9(DOB[9]), .DOB8(DOB[8]), .DOB7(DOB[7]), .DOB6(DOB[6]), .DOB5(DOB[5]), .DOB4(DOB[4]), .DOB3(DOB[3]), .DOB2(DOB[2]), .DOB1(DOB[1]), .DOB0(DOB[0]));
-
-  always begin
-    #5
-    CLKA <= !CLKA;
-    CLKB <= !CLKB;
-  end
-
-  initial begin
-    $dumpfile("tb_DP16KD_18b_sync_nowriteout_unregistered");
-    $dumpvars(0, tb_DP16KD_18b_sync_nowriteout_unregistered);
-    #10
-    // Write to lowest and highest addrs, read back from the other port.
-    TESTNAME="SIMPLE WRITE/READ 1";
-    ADA=0; DIA=42; CEA=1; WEA=1; // Write min addr
-    ADB=1023; DIB=18'h3FFFF; CEB=1; WEB=1; // write max addr
-    #10
-    ADA=1023; DIA=0; CEA=1; WEA=0; // Read max addr
-    ADB=0;    DIB=0; CEB=1; WEB=0; // Read min addr
-    #10
-    // Swap values around, read back from other port.
-    TESTNAME="SIMPLE WRITE/READ 2";
-    ADA=1023; DIA=42;        CEA=1; WEA=1; // Write max addr
-    ADB=0;    DIB=18'h3FFFF; CEB=1; WEB=1; // Write min addr
-    #10
-    ADA=0;    DIA=0; CEA=1; WEA=0; // Read min addr
-    ADB=1023; DIB=0; CEB=1; WEB=0; // Read max addr
-    #10
-    // No change when reading and not enabled
-    TESTNAME="NOT ENABLED";
-    ADA=1023; DIA=0; CEA=0; WEA=0;
-    ADB=0;    DIA=0; CEB=0; WEB=0;
-    #10
-    // Output changes again with chip enabled
-    CEA=1;
-    CEB=1;
-    #10
-    // Same if another chip is selected
-    TESTNAME="NOT SELECTED";
-    ADA=1023; DIA=0; WEA=0; CSA=3;
-    ADB=0;    DIB=0; WEB=0; CSB=2;
-    #10
-    // Output changes again with chip enabled
-    CSA=0;
-    CSB=0;
-    #10
-    // Reset clears regs, overrules input, doesn't affect other port,
-    // doesn't affect memory contents.
-    TESTNAME="RESET A";
-    ADA=0; RSTA=1;
-    #10
-    RSTA=0;
-    #10
-    TESTNAME="RESET B";
-    ADB=1023; RSTB=1;
-    #10
-    RSTB=0;
-    #10
-    // Write-write conflict writes undef value
-    TESTNAME="WRITE/WRITE CONFLICT";
-    ADA=0; DIA=0;         WEA=1;
-    ADB=0; DIB=18'h3FFFF; WEB=1;
-    #10
-    WEA=0;
-    WEB=0;
-    #10
-    // Write-write conflict writes undef value
-    TESTNAME="A READ/B WRITE CONFLICT";
-    ADA=0; DIA=0;         WEA=0;
-    ADB=0; DIB=18'h3FFFF; WEB=1;
-    #10
-    WEA=0;
-    WEB=0;
-    #10
-    // Write-write conflict writes undef value
-    TESTNAME="A WRITE/B READ CONFLICT";
-    ADA=0; DIA=0;         WEA=1;
-    ADB=0; DIB=18'h3FFFF; WEB=0;
-    #10
-    WEA=0;
-    WEB=0;
-    #10
-    TESTNAME=240'bx;
-    #10
-    $finish;
-  end
-endmodule
--- a/sim/tb/tb_DP16KD_sync_same_width.v
+++ b/sim/tb/tb_DP16KD_sync_same_width.v
@ -0,0 +1,197 @@
+module tb#(
+  parameter DATA_WIDTH_A=18,
+  parameter DATA_WIDTH_B=18,
+  parameter ADDR_WIDTH_A=10,
+  parameter ADDR_WIDTH_B=10
+);
+  localparam ADDR_MAX_A = 2**ADDR_WIDTH_A - 1;
+  localparam ADDR_MAX_B = 2**ADDR_WIDTH_B - 1;
+  localparam DATA_MAX_A = 2**DATA_WIDTH_A - 1;
+  localparam DATA_MAX_B = 2**DATA_WIDTH_B - 1;
+
+  reg CLKA=0, RSTA=0, CEA=0, OCEA=1, WEA=0;
+  reg CLKB=0, RSTB=0, CEB=0, OCEB=0, WEB=0;
+  reg [2:0] CSA=0, CSB=0;
+  reg [13:0] ADA;
+  reg [13:0] ADB;
+  reg [17:0] DIA;
+  reg [17:0] DIB;
+  wire [17:0] DOA;
+  wire [17:0] DOB;
+  reg [17:0] WANTA;
+  reg [17:0] WANTB;
+  wire BADA = DOA !== WANTA;
+  wire BADB = DOB !== WANTB;
+  reg [239:0] TESTNAME;
+
+  wire [17:0] UNDEFA = {DATA_WIDTH_A{1'bx}};
+  wire [17:0] UNDEFB = {DATA_WIDTH_B{1'bx}};
+
+  DP16KD#(.WRITEMODE_A("NORMAL"),
+          .WRITEMODE_B("NORMAL"),
+          .REGMODE_A("NOREG"),
+          .REGMODE_B("NOREG"),
+          .RESETMODE("SYNC"),
+          .ASYNC_RESET_RELEASE("SYNC"),
+          .DATA_WIDTH_A(DATA_WIDTH_A),
+          .DATA_WIDTH_B(DATA_WIDTH_B)
+          ) uut(.CLKA(CLKA), .RSTA(RSTA), .CEA(CEA), .OCEA(OCEA), .WEA(WEA),
+                .CSA2(CSA[2]), .CSA1(CSA[1]), .CSA0(CSA[0]),
+                .ADA13(ADA[13]), .ADA12(ADA[12]), .ADA11(ADA[11]), .ADA10(ADA[10]), .ADA9(ADA[9]), .ADA8(ADA[8]), .ADA7(ADA[7]), .ADA6(ADA[6]), .ADA5(ADA[5]), .ADA4(ADA[4]), .ADA3(ADA[3]), .ADA2(ADA[2]), .ADA1(ADA[1]), .ADA0(ADA[0]),
+                .DIA17(DIA[17]), .DIA16(DIA[16]), .DIA15(DIA[15]), .DIA14(DIA[14]), .DIA13(DIA[13]), .DIA12(DIA[12]), .DIA11(DIA[11]), .DIA10(DIA[10]), .DIA9(DIA[9]), .DIA8(DIA[8]), .DIA7(DIA[7]), .DIA6(DIA[6]), .DIA5(DIA[5]), .DIA4(DIA[4]), .DIA3(DIA[3]), .DIA2(DIA[2]), .DIA1(DIA[1]), .DIA0(DIA[0]),
+                .DOA17(DOA[17]), .DOA16(DOA[16]), .DOA15(DOA[15]), .DOA14(DOA[14]), .DOA13(DOA[13]), .DOA12(DOA[12]), .DOA11(DOA[11]), .DOA10(DOA[10]), .DOA9(DOA[9]), .DOA8(DOA[8]), .DOA7(DOA[7]), .DOA6(DOA[6]), .DOA5(DOA[5]), .DOA4(DOA[4]), .DOA3(DOA[3]), .DOA2(DOA[2]), .DOA1(DOA[1]), .DOA0(DOA[0]),
+
+                .CLKB(CLKB), .RSTB(RSTB), .CEB(CEB), .OCEB(OCEB), .WEB(WEB),
+                .CSB2(CSB[2]), .CSB1(CSB[1]), .CSB0(CSB[0]),
+                .ADB13(ADB[13]), .ADB12(ADB[12]), .ADB11(ADB[11]), .ADB10(ADB[10]), .ADB9(ADB[9]), .ADB8(ADB[8]), .ADB7(ADB[7]), .ADB6(ADB[6]), .ADB5(ADB[5]), .ADB4(ADB[4]), .ADB3(ADB[3]), .ADB2(ADB[2]), .ADB1(ADB[1]), .ADB0(ADB[0]),
+                .DIB17(DIB[17]), .DIB16(DIB[16]), .DIB15(DIB[15]), .DIB14(DIB[14]), .DIB13(DIB[13]), .DIB12(DIB[12]), .DIB11(DIB[11]), .DIB10(DIB[10]), .DIB9(DIB[9]), .DIB8(DIB[8]), .DIB7(DIB[7]), .DIB6(DIB[6]), .DIB5(DIB[5]), .DIB4(DIB[4]), .DIB3(DIB[3]), .DIB2(DIB[2]), .DIB1(DIB[1]), .DIB0(DIB[0]),
+                .DOB17(DOB[17]), .DOB16(DOB[16]), .DOB15(DOB[15]), .DOB14(DOB[14]), .DOB13(DOB[13]), .DOB12(DOB[12]), .DOB11(DOB[11]), .DOB10(DOB[10]), .DOB9(DOB[9]), .DOB8(DOB[8]), .DOB7(DOB[7]), .DOB6(DOB[6]), .DOB5(DOB[5]), .DOB4(DOB[4]), .DOB3(DOB[3]), .DOB2(DOB[2]), .DOB1(DOB[1]), .DOB0(DOB[0]));
+
+  always begin
+    #5
+    CLKA <= !CLKA;
+    CLKB <= !CLKB;
+  end
+
+  initial begin
+    $dumpfile("tb");
+    $dumpvars(0, tb);
+    #10
+
+    // Write to lowest and highest addrs, read back from the other port.
+    TESTNAME="SIMPLE WRITE/READ 1";
+    ADA=0;          DIA=1;          CEA=1; WEA=1; // Write min addr
+    ADB=ADDR_MAX_B; DIB=DATA_MAX_B; CEB=1; WEB=1; // write max addr
+    #5
+    WANTA=UNDEFA;
+    WANTB=UNDEFB;
+    #5
+
+    ADA=ADDR_MAX_A; DIA=0; CEA=1; WEA=0; // Read max addr
+    ADB=0;          DIB=0; CEB=1; WEB=0; // Read min addr
+    #5
+    WANTA=DATA_MAX_A;
+    WANTB=1;
+    #5
+
+    // Swap values around, read back from other port.
+    TESTNAME="SIMPLE WRITE/READ 2";
+    ADA=ADDR_MAX_A-1; DIA=DATA_MAX_A-1; CEA=1; WEA=1; // Write max addr
+    ADB=1;            DIB=2;            CEB=1; WEB=1; // Write min addr
+    #5
+    WANTA=UNDEFA;
+    WANTB=UNDEFB;
+    #5
+
+    ADA=1;            DIA=0; CEA=1; WEA=0; // Read min addr
+    ADB=ADDR_MAX_B-1; DIB=0; CEB=1; WEB=0; // Read max addr
+    #5
+    WANTA=2;
+    WANTB=DATA_MAX_B-1;
+    #5
+
+    // No change when reading and not enabled
+    TESTNAME="NOT ENABLED";
+    ADA=0; DIA=0; CEA=0; WEA=0;
+    ADB=0; DIA=0; CEB=0; WEB=0;
+    #10
+
+    // Output changes again with chip enabled
+    CEA=1;
+    CEB=1;
+    #5
+    WANTA=1;
+    WANTB=1;
+    #5
+
+    // Same if another chip is selected
+    TESTNAME="NOT SELECTED";
+    ADA=ADDR_MAX_A; DIA=0; WEA=0; CSA=3;
+    ADB=ADDR_MAX_B; DIB=0; WEB=0; CSB=2;
+    #10
+
+    // Output changes again with chip enabled
+    CSA=0;
+    CSB=0;
+    #5
+    WANTA=DATA_MAX_A;
+    WANTB=DATA_MAX_B;
+    #5
+
+    // Reset clears regs, overrules input, doesn't affect other port,
+    // doesn't affect memory contents.
+    TESTNAME="RESET A";
+    ADA=0; RSTA=1;
+    #5
+    WANTA=0;
+    #5
+
+    RSTA=0;
+    #5
+    WANTA=1;
+    #5;
+
+    TESTNAME="RESET B";
+    ADB=0; RSTB=1;
+    #5
+    WANTB=0;
+    #5
+
+    RSTB=0;
+    #5
+    WANTB=1;
+    #5
+
+    // Write-write conflict writes undef value
+    TESTNAME="WRITE/WRITE CONFLICT";
+    ADA=0; DIA=0;          WEA=1;
+    ADB=0; DIB=DATA_MAX_B; WEB=1;
+    #5
+    WANTA=UNDEFA;
+    WANTB=UNDEFB;
+    #5
+
+    WEA=0;
+    WEB=0;
+    #5
+    WANTA=UNDEFA;
+    WANTB=UNDEFB;
+    #5
+
+    // Read-write conflict reads undef value
+    TESTNAME="A READ/B WRITE CONFLICT";
+    ADA=0; DIA=0;          WEA=0;
+    ADB=0; DIB=DATA_MAX_B; WEB=1;
+    #5
+    WANTA=UNDEFA;
+    WANTB=UNDEFB;
+    #5
+
+    WEA=0;
+    WEB=0;
+    #5
+    WANTA=DATA_MAX_A;
+    WANTB=DATA_MAX_B;
+    #5
+
+    // Write-read conflict writes undef value
+    TESTNAME="A WRITE/B READ CONFLICT";
+    ADA=0; DIA=0;          WEA=1;
+    ADB=0; DIB=DATA_MAX_B; WEB=0;
+    #5
+    WANTA=UNDEFA;
+    WANTB=UNDEFB;
+    #5
+
+    WEA=0;
+    WEB=0;
+    #5
+    WANTA=0;
+    WANTB=0;
+    #5
+
+    TESTNAME=240'bx;
+    #10
+    $finish;
+  end
+endmodule
--- a/sim/tb_cfg.gtkw
+++ b/sim/tb_cfg.gtkw
@ -0,0 +1,73 @@
+[*]
+[*] GTKWave Analyzer v3.3.120 (w)1999-2024 BSI
+[*] Sat Aug 31 03:16:28 2024
+[*]
+[dumpfile] "WORKING_DIR/VCDFILE"
+[dumpfile_mtime] "Sat Aug 31 03:12:41 2024"
+[dumpfile_size] 28485
+[savefile] "WORKING_DIR/GTKWFILE"
+[timestart] 0
+[size] 2556 660
+[pos] -1 -1
+*-4.261485 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] tb.
+[treeopen] tb.uut.
+[sst_width] 282
+[signals_width] 150
+[sst_expanded] 1
+[sst_vpaned_height] 164
+@820
+[color] 5
+tb.TESTNAME[239:0]
+[color] 5
+tb.WRITEMODE_A
+@821
+[color] 5
+tb.WRITEMODE_B
+@200
+-
+@28
+tb.RSTA
+tb.CEA
+tb.CSA[2:0]
+@22
+tb.ADA[13:0]
+tb.DIA[17:0]
+@28
+[color] 3
+tb.WEA
+[color] 7
+tb.CLKA
+@22
+tb.DOA[17:0]
+[color] 2
+tb.WANTA[17:0]
+@28
+[color] 1
+tb.BADA
+@200
+-
+-
+@28
+tb.RSTB
+@29
+tb.CEB
+@28
+tb.CSB[2:0]
+@22
+tb.ADB[13:0]
+tb.DIB[17:0]
+@28
+[color] 3
+tb.WEB
+[color] 7
+tb.CLKB
+@22
+tb.DOB[17:0]
+[color] 2
+tb.WANTB[17:0]
+@28
+[color] 1
+tb.BADB
+[pattern_trace] 1
+[pattern_trace] 0
--- a/tasks.py
+++ b/tasks.py
@ -155,6 +155,7 @@ def synth(c, target):
    print(f"     Log : {yosys_log}")
    print(f"    Flat : {yosys_preprocessed}")
    print(f"Compiled : {yosys_compiled}")
+    print(f"     Dot : {yosys_preprocessed_graph}.dot")

    pin_map = target.parent / "pin_map.lpf"
    if not pin_map.is_file():
Author	SHA1	Message	Date
David Anderson	119eeceaef	Add some early testing harness for the sim DP16KD	2024-08-30 22:14:10 -07:00
David Anderson	a4a10becbf	tasks.py: print one more intermediate output path	2024-08-30 20:06:36 -07:00
David Anderson	a0892fefcd	sim/tb: add "bad" signals to make it easier to see wrong outputs	2024-08-30 20:00:11 -07:00
David Anderson	b913afd416	sim/tb: add wanted output signal, to help see incorrect outputs	2024-08-30 19:56:08 -07:00