Yosys doesn't understand Verilog-2001 port aliases. Unfortunately
bsc uses those to represent inout ports because it's the only way
to represent a particular kind of shared bus in Verilog source code.
Thankfully, a kind soul at Bluespec Inc made a perl script that
transforms the port alias construct into regular verilog-1995, which
works fine in cases like mine where the only user of the inout port
is a TriState module which tears it apart into separate
input/output/enable signals for the rest of bsc to work with.
