Commit Graph

111 Commits

Author SHA1 Message Date
David Anderson e64b990f80 lib: fix port B reset wiring for ECP5_RAM 2024-08-17 16:38:52 -07:00
David Anderson 8d2261e245 lib: initial implementation of an ECP5 EBR primitive
Only the core unconditioned primitive right now, and still needs refining.
2024-08-17 15:43:36 -07:00
David Anderson db30e4a23f tasks.py: prettify output, support running partial synthesis
Partial synth is handy when writing gnarly Bluespec modules, because it
lets you inspect the Verilog output of the Bluespec compiler as well as
Yosys's compile output at various stages of synthesis, to see if things
are being produced the way you expect.
2024-08-17 15:41:21 -07:00
David Anderson e6fa717507 Experiment comparing bsc-contrib's video timing generator with brute force
Brute force is a naively written state machine that combines both horizontal
and vertical timings into one, in a way that unrolls comically badly. It's
obviously uncompetitive as-is, but I wanted to use that as a starting point
to see how much bsc and yosys would still be able to cope with it.

The result: the worse code takes much longer for bluespec to evaluate, and it
consumes ~4x the amount of logic elements after synthesis. Less terrible than
I expected, to be honest!
2024-08-15 00:22:51 -07:00
David Anderson dad128b56b Fix up some bugs in the Invoke script. 2024-08-15 00:22:30 -07:00
David Anderson 2efb40fa3d Requirements.md: fix image insertion syntax 2024-08-14 09:44:14 -07:00
David Anderson 39e17f8e42 lib: add test helpers for timeouts and sequential test running 2024-08-14 09:39:42 -07:00
David Anderson 730d11ecea Add tentative requirements document to capture requests. 2024-08-14 09:39:42 -07:00
David Anderson e83f3a993c add a simple build/test script 2024-08-14 09:39:42 -07:00
David Anderson 3111d069e6 Initial basic files 2024-08-13 22:24:20 -07:00
David Anderson 8f0e0dbbad initial commit 2024-08-12 00:36:17 -07:00